Area Comparison of CHERIoT and PMP in Ibex

2025-05-13

AI Summary

This work evaluates the area overhead of CHERIoT capability hardware extensions and Physical Memory Protection (PMP) on the Ibex RISC-V core for security-critical embedded systems—particularly IoT devices. Using the FreePDK45 process, we perform fine-grained RTL synthesis and gate-equivalent (kGE) area decomposition under a unified open-source core and implementation flow—the first such comparative analysis. Results show PMP incurs 24 kGE overhead (+42% over baseline core area), while CHERIoT adds 33 kGE (+57%). However, at the OpenTitan Earl Grey SoC level, their respective overheads shrink to only 0.6% and 1.0%, markedly lower than core-level increases. This study is the first to quantitatively characterize the disparity in area cost between microarchitectural and SoC-level integration of memory-safety extensions. It demonstrates that both mechanisms remain practically viable in resource-constrained embedded environments, establishing critical area benchmarks for deploying RISC-V memory safety hardware.

Technology Category

• Machine Learning: Hardware-aware ML
• Application Domains: Internet of Things, Sensor Networks & Smart Cities
• Knowledge Representation and Reasoning: Computational Complexity of Reasoning

Application Category

• Security and Privacy: Large-scale security measurements
• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Responsible Web: Data and user privacy-enhancing technologies for the Web

Abstract

Memory safety is a critical concern for modern embedded systems, particularly in security-sensitive applications. This paper explores the area impact of adding memory safety extensions to the Ibex RISC-V core, focusing on physical memory protection (PMP) and Capability Hardware Extension to RISC-V for Internet of Things (CHERIoT). We synthesise the extended Ibex cores using a commercial tool targeting the open FreePDK45 process and provide a detailed area breakdown and discussion of the results. The PMP configuration we consider is one with 16 PMP regions. We find that the extensions increase the core size by 24 thousand gate-equivalent (kGE) for PMP and 33 kGE for CHERIoT. The increase is mainly due to the additional state required to store information about protected memory. While this increase amounts to 42% for PMP and 57% for CHERIoT in Ibex's area, its effect on the overall system is minimal. In a complete system-on-chip (SoC), like the secure microcontroller OpenTitan Earl Grey, where the core represents only a fraction of the total area, the estimated system-wide overhead is 0.6% for PMP and 1% for CHERIoT. Given the security benefits these extensions provide, the area trade-off is justified, making Ibex a compelling choice for secure embedded applications.

Problem

• Assessing area impact of memory safety extensions on Ibex RISC-V core
• Comparing PMP and CHERIoT overhead in gate-equivalent (kGE) terms
• Evaluating system-wide area trade-offs for secure embedded applications

Innovation

• Compares CHERIoT and PMP memory safety extensions
• Synthesizes extended Ibex cores using FreePDK45
• Measures area impact as 24kGE and 33kGE