Scalable AXI4 Transaction Monitoring for Mixed-Criticality SoCs: From Phase-Level Precision to ID-Level Efficiency
为了解决AXI4协议缺乏超时机制导致的死锁问题，本文提出了一种可配置硬件IP，通过三种不同粒度的设计（PLT、CLT和ILT）来监测并恢复互联活动。
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Area Comparison of CHERIoT and PMP in Ibex
This work evaluates the area overhead of CHERIoT capability hardware extensions and Physical Memory Protection (PMP) on the Ibex RISC-V core for security-critical embedded systems—particularly IoT devices. Using the FreePDK45 process, we perform fine-grained RTL synthesis and gate-equivalent (kGE) area decomposition under a unified open-source core and implementation flow—the first such comparative analysis. Results show PMP incurs 24 kGE overhead (+42% over baseline core area), while CHERIoT adds 33 kGE (+57%). However, at the OpenTitan Earl Grey SoC level, their respective overheads shrink to only 0.6% and 1.0%, markedly lower than core-level increases. This study is the first to quantitatively characterize the disparity in area cost between microarchitectural and SoC-level integration of memory-safety extensions. It demonstrates that both mechanisms remain practically viable in resource-constrained embedded environments, establishing critical area benchmarks for deploying RISC-V memory safety hardware.
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Scalable AXI4 Transaction Monitoring for Mixed-Criticality SoCs: From Phase-Level Precision to ID-Level Efficiency
为了解决AXI4协议缺乏超时机制导致的死锁问题，本文提出了一种可配置硬件IP，通过三种不同粒度的设计（PLT、CLT和ILT）来监测并恢复互联活动。
0 citationsRead paper
Area Comparison of CHERIoT and PMP in Ibex
This work evaluates the area overhead of CHERIoT capability hardware extensions and Physical Memory Protection (PMP) on the Ibex RISC-V core for security-critical embedded systems—particularly IoT devices. Using the FreePDK45 process, we perform fine-grained RTL synthesis and gate-equivalent (kGE) area decomposition under a unified open-source core and implementation flow—the first such comparative analysis. Results show PMP incurs 24 kGE overhead (+42% over baseline core area), while CHERIoT adds 33 kGE (+57%). However, at the OpenTitan Earl Grey SoC level, their respective overheads shrink to only 0.6% and 1.0%, markedly lower than core-level increases. This study is the first to quantitatively characterize the disparity in area cost between microarchitectural and SoC-level integration of memory-safety extensions. It demonstrates that both mechanisms remain practically viable in resource-constrained embedded environments, establishing critical area benchmarks for deploying RISC-V memory safety hardware.
0 citationsRead paper