ChipletQuake: On-die Digital Impedance Sensing for Chiplet and Interposer Verification

2025-04-28

AI Summary

To address security threats—including physical tampering, hardware Trojans, and passive malicious circuit insertion—arising from the horizontal hardware supply chain in chiplet-based architectures, this paper proposes an on-chip impedance-sensing method requiring no additional hardware or dedicated interfaces. The approach enables non-intrusive, zero-overhead detection of interconnects and adjacent chiplets by real-time monitoring of dynamic impedance variations in the power delivery network (PDN). We introduce the first FPGA-native PDN impedance sensing mechanism, leveraging intrinsic digital logic resources and integrating timing-sensitive side-channel feature extraction with dynamic response modeling. Evaluated on an FPGA-based chiplet platform, the method detects sub-micrometer-scale hardware Trojans and metal-layer alterations with a false positive rate <0.3% and detection latency <100 ns. It is fully compatible with advanced packaging standards such as UCIe.

Technology Category

• Machine Learning: Hardware-aware ML
• Application Domains: Internet of Things, Sensor Networks & Smart Cities
• Constraint Satisfaction and Optimization: Distributed CSP/Optimization

Application Category

• Security and Privacy: Large-scale security measurements
• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs

Abstract

The increasing complexity and cost of manufacturing monolithic chips have driven the semiconductor industry toward chiplet-based designs, where smaller and modular chiplets are integrated onto a single interposer. While chiplet architectures offer significant advantages, such as improved yields, design flexibility, and cost efficiency, they introduce new security challenges in the horizontal hardware manufacturing supply chain. These challenges include risks of hardware Trojans, cross-die side-channel and fault injection attacks, probing of chiplet interfaces, and intellectual property theft. To address these concerns, this paper presents extit{ChipletQuake}, a novel on-chiplet framework for verifying the physical security and integrity of adjacent chiplets during the post-silicon stage. By sensing the impedance of the power delivery network (PDN) of the system, extit{ChipletQuake} detects tamper events in the interposer and neighboring chiplets without requiring any direct signal interface or additional hardware components. Fully compatible with the digital resources of FPGA-based chiplets, this framework demonstrates the ability to identify the insertion of passive and subtle malicious circuits, providing an effective solution to enhance the security of chiplet-based systems. To validate our claims, we showcase how our framework detects Hardware Trojan and interposer tampering.

Problem

• Detects hardware Trojans in chiplet-based designs
• Identifies interposer tampering without additional hardware
• Ensures physical security of adjacent chiplets post-silicon

Innovation

• On-die digital impedance sensing for security
• Detects tamper via power delivery network impedance
• FPGA-compatible without additional hardware components