Hierarchical Decoupling Capacitor Optimization for Power Distribution Network of 2.5D ICs with Co-Analysis of Frequency and Time Domains Based on Deep Reinforcement Learning

2024-07-02

arXiv.org

AI Summary

In 2.5D ICs, conventional frequency-domain impedance optimization for power delivery networks (PDNs) fails to simultaneously ensure time-domain voltage integrity due to coupling between small-signal noise and synchronous switching noise (SSN). Method: This paper proposes the first dual-domain collaborative hierarchical decoupling capacitor (decap) optimization method, integrating frequency-domain impedance modeling with time-domain transient simulation feedback within a two-stage deep reinforcement learning framework to jointly optimize decap placement across chip and silicon interposer PDNs. Contribution/Results: The method jointly minimizes impedance magnitude and time-domain voltage violation integral (VVI), achieving robust PDN design without compromising layout simplicity. Experiments demonstrate a 37% improvement in SSN suppression over conventional frequency-domain approaches, along with simultaneous reductions in both voltage violation amplitude and duration.

Technology Category

• Constraint Satisfaction and Optimization: Distributed CSP/Optimization
• Computer Vision: Learning & Optimization for CV
• Search and Optimization: Distributed Search

Application Category

• Search and Retrieval-Augmented AI: Vertical and domain-specific search
• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs

Abstract

With the growing need for higher memory bandwidth and computation density, 2.5D design, which involves integrating multiple chiplets onto an interposer, emerges as a promising solution. However, this integration introduces significant challenges due to increasing data rates and a large number of I/Os, necessitating advanced optimization of the power distribution networks (PDNs) both on-chip and on-interposer to mitigate the small signal noise and simultaneous switching noise (SSN). Traditional PDN optimization strategies in 2.5D systems primarily focus on reducing impedance by integrating decoupling capacitors (decaps) to lessen small signal noises. Unfortunately, relying solely on frequency-domain analysis has been proven inadequate for addressing coupled SSN, as indicated by our experimental results. In this work, we introduce a novel two-phase optimization flow using deep reinforcement learning to tackle both the on-chip small signal noise and SSN. Initially, we optimize the impedance in the frequency domain to maintain the small signal noise within acceptable limits while avoiding over-design. Subsequently, in the time domain, we refine the PDN to minimize the voltage violation integral (VVI), a more accurate measure of SSN severity. To the best of our knowledge, this is the first dual-domain optimization strategy that simultaneously addresses both the small signal noise and SSN propagation through strategic decap placement in on-chip and on-interposer PDNs, offering a significant step forward in the design of robust PDNs for 2.5D integrated systems.

Problem

• Optimize power distribution networks for 2.5D ICs
• Address small signal noise and switching noise
• Use deep reinforcement learning for dual-domain analysis

Innovation

• Deep reinforcement learning for PDN optimization
• Dual-domain frequency and time analysis
• Strategic decap placement for noise reduction