E-morphic: Scalable Equality Saturation for Structural Exploration in Logic~Synthesis

2025-04-15

AI Summary

In logic synthesis, structural optimization prior to technology mapping suffers from inherent structural biases in conventional flows and scalability limitations of equality saturation (ES). This work pioneers the integration of ES into the resynthesis phase following standard technology-independent optimization. We introduce (i) a bidirectional direct translation mechanism between e-graphs and circuits, (ii) a dynamic solution-space pruning strategy to mitigate exponential growth, and (iii) a simulated-annealing-driven method for high-quality e-graph extraction—enabling parallel, bias-free circuit structure exploration. Evaluated on the EPFL large-scale benchmark suite, our approach achieves, on average, 12.54% area reduction and 7.29% delay reduction over ABC’s state-of-the-art delay-optimization flow, significantly improving both the effectiveness and efficiency of pre-mapping optimization.

Technology Category

• Search and Optimization: Sampling/Simulation-based Search
• Constraint Satisfaction and Optimization: Satisfiability
• Machine Learning: Optimization

Application Category

• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Semantics and Knowledge: Scalable techniques for the creation, curation, publication, maintenance, and consumption of large, Web-based, structured, reusable, knowledge graphs and ontologies

Abstract

In technology mapping, the quality of the final implementation heavily relies on the circuit structure after technology-independent optimization. Recent studies have introduced equality saturation as a novel optimization approach. However, its efficiency remains a hurdle against its wide adoption in logic synthesis. This paper proposes a highly scalable and efficient framework named E-morphic. It is the first work that employs equality saturation for resynthesis after conventional technology-independent logic optimizations, enabling structure exploration before technology mapping. Powered by several key enhancements to the equality saturation framework, such as direct e-graph-circuit conversion, solution-space pruning, and simulated annealing for e-graph extraction, this approach not only improves the scalability and extraction efficiency of e-graph rewriting but also addresses the structural bias issue present in conventional logic synthesis flows through parallel structural exploration and resynthesis. Experiments show that, compared to the state-of-the-art delay optimization flow in ABC, E-morphic on average achieves 12.54% area saving and 7.29% delay reduction on the large-scale circuits in the EPFL benchmark.

Problem

• Enhances scalability of equality saturation in logic synthesis
• Addresses structural bias in conventional synthesis flows
• Improves area and delay in circuit optimization

Innovation

• Employs equality saturation for resynthesis
• Enhances e-graph with pruning and annealing
• Enables parallel structural exploration efficiently