OSIRIS: Bridging Analog Circuit Design and Machine Learning with Scalable Dataset Generation

2026-01-27

AI Summary

This work addresses the challenge of analog integrated circuit (IC) design automation, which is hindered by the strong coupling among physical layout, parasitic effects, and circuit performance, as well as the lack of high-quality open-source datasets for machine learning research. To bridge this gap, the authors propose the first large-scale, parasitic-aware dataset generation framework tailored for analog ICs. By automating parameter sweeps, parasitic extraction, and post-layout simulation, they construct an open-source dataset comprising 87,100 circuit variants. The framework further integrates a reinforcement learning baseline to enable an end-to-end optimization loop. This contribution establishes a scalable data foundation and algorithmic validation platform for data-driven analog electronic design automation (EDA), significantly advancing the application of machine learning in automated analog circuit design.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Analogy
• Search and Optimization: Sampling/Simulation-based Search

Application Category

• Economics, Online Markets and Human Computation: Data quality aspects of human-annotated datasets
• Web Mining and Content Analysis: Web data generation and simulation
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs

Abstract

The automation of analog integrated circuit (IC) design remains a longstanding challenge, primarily due to the intricate interdependencies among physical layout, parasitic effects, and circuit-level performance. These interactions impose complex constraints that are difficult to accurately capture and optimize using conventional design methodologies. Although recent advances in machine learning (ML) have shown promise in automating specific stages of the analog design flow, the development of holistic, end-to-end frameworks that integrate these stages and iteratively refine layouts using post-layout, parasitic-aware performance feedback is still in its early stages. Furthermore, progress in this direction is hindered by the limited availability of open, high-quality datasets tailored to the analog domain, restricting both the benchmarking and the generalizability of ML-based techniques. To address these limitations, we present OSIRIS, a scalable dataset generation pipeline for analog IC design. OSIRIS systematically explores the design space of analog circuits while producing comprehensive performance metrics and metadata, thereby enabling ML-driven research in electronic design automation (EDA). In addition, we release a dataset consisting of 87,100 circuit variations generated with OSIRIS, accompanied by a reinforcement learning (RL)-based baseline method that exploits OSIRIS for analog design optimization.

Problem

• analog IC design
• machine learning
• dataset generation
• parasitic effects
• design automation

Innovation

• scalable dataset generation
• parasitic-aware analog design
• machine learning for EDA
• reinforcement learning optimization
• analog IC automation