Binary Neural Network Implementation for Handwritten Digit Recognition on FPGA

2025-12-22

AI Summary

Handwritten digit recognition on resource-constrained, low-power embedded FPGA platforms demands high real-time performance and predictable timing. Method: This work proposes a fully hand-coded Verilog binary neural network (BNN) inference accelerator, eschewing high-level synthesis tools. A custom hardware architecture is designed with bit-level optimizations and fine-grained timing control to achieve stable operation at 80 MHz. The end-to-end flow—including MNIST training, binarization, and hardware mapping—is deployed on a Xilinx Artix-7 FPGA. Contribution/Results: We present the first fully RTL-level, manually designed BNN accelerator that jointly optimizes reconfigurability, resource efficiency, and deployment transparency. Experimental results demonstrate 84% classification accuracy on MNIST, significantly reduced power consumption, and highly deterministic timing behavior. To foster reproducibility and further research, we publicly release both the complete training scripts and the synthesizable RTL code.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Computer Vision: Learning & Optimization for CV

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications
• User Modeling, Personalization and Recommendation: On-Device user modeling, personalization, and recommendation
• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs

Abstract

Binary neural networks provide a promising solution for low-power, high-speed inference by replacing expensive floating-point operations with bitwise logic. This makes them well-suited for deployment on resource-constrained platforms such as FPGAs. In this study, we present a fully custom BNN inference accelerator for handwritten digit recognition, implemented entirely in Verilog without the use of high-level synthesis tools. The design targets the Xilinx Artix-7 FPGA and achieves real-time classification at 80,MHz with low power consumption and predictable timing. Simulation results demonstrate 84% accuracy on the MNIST test set and highlight the advantages of manual HDL design for transparent, efficient, and flexible BNN deployment in embedded systems. The complete project including training scripts and Verilog source code are available at GitHub repo for reproducibility and future development.

Problem

• Implementing a BNN accelerator for handwritten digit recognition on FPGA.
• Achieving real-time classification with low power consumption on Artix-7 FPGA.
• Providing a transparent and efficient BNN deployment solution for embedded systems.

Innovation

• Custom Verilog BNN accelerator for FPGA
• Manual HDL design ensures transparent efficient deployment
• Real-time classification at 80 MHz with low power