Dec 22, 2025
Handwritten digit recognition on resource-constrained, low-power embedded FPGA platforms demands high real-time performance and predictable timing.
Method: This work proposes a fully hand-coded Verilog binary neural network (BNN) inference accelerator, eschewing high-level synthesis tools. A custom hardware architecture is designed with bit-level optimizations and fine-grained timing control to achieve stable operation at 80 MHz. The end-to-end flow—including MNIST training, binarization, and hardware mapping—is deployed on a Xilinx Artix-7 FPGA.
Contribution/Results: We present the first fully RTL-level, manually designed BNN accelerator that jointly optimizes reconfigurability, resource efficiency, and deployment transparency. Experimental results demonstrate 84% classification accuracy on MNIST, significantly reduced power consumption, and highly deterministic timing behavior. To foster reproducibility and further research, we publicly release both the complete training scripts and the synthesizable RTL code.