Implementation and Analysis of Thermometer Encoding in DWN FPGA Accelerators

2025-12-17

AI Summary

The hardware overhead of thermometer encoding (TE) in differential weightless neural network (DWN) accelerators on FPGAs has remained unquantified, hindering accurate resource estimation and optimization. Method: This work introduces the first explicit analytical model of TE overhead and integrates it into the DWN hardware generation flow, enabling systematic logic-resource analysis of TE. Contribution/Results: Experiments reveal that TE dominates resource consumption in small-scale DWNs, increasing LUT utilization by up to 3.20×—identifying it as a critical bottleneck. By enabling encoding-aware co-design, this study fills a key gap in modeling and evaluating encoding overhead in practical DWN deployment, providing the first quantitative foundation for joint optimization of TE and compute units. Validation on the Jet Substructure Classification benchmark confirms the model’s accuracy and practical relevance.

Technology Category

• Machine Learning: Hardware-aware ML
• Knowledge Representation and Reasoning: Computational Complexity of Reasoning
• Search and Optimization: Distributed Search

Application Category

• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines

Abstract

Fully parallel neural network accelerators on field-programmable gate arrays (FPGAs) offer high throughput for latency-critical applications but face hardware resource constraints. Weightless neural networks (WNNs) efficiently replace arithmetic with logic-based inference. Differential weightless neural networks (DWN) further optimize resource usage by learning connections between encoders and LUT layers via gradient-based training. However, DWNs rely on thermometer encoding, and the associated hardware cost has not been fully evaluated. We present a DWN hardware generator that includes thermometer encoding explicitly. Experiments on the Jet Substructure Classification (JSC) task show that encoding can increase LUT usage by up to 3.20$ imes$, dominating costs in small networks and highlighting the need for encoding-aware hardware design in DWN accelerators.

Problem

• Evaluates hardware cost of thermometer encoding in DWN FPGA accelerators
• Analyzes encoding's impact on LUT usage in weightless neural networks
• Proposes encoding-aware hardware design for resource-constrained FPGA applications

Innovation

• DWN hardware generator includes thermometer encoding
• Thermometer encoding increases LUT usage significantly
• Encoding-aware design needed for DWN FPGA accelerators