FERIVer: An FPGA-assisted Emulated Framework for RTL Verification of RISC-V Processors

2025-04-07

AI Summary

Processor verification faces an efficiency bottleneck between fast but imprecise instruction-level simulation and accurate yet extremely slow RTL simulation. This paper proposes an FPGA-accelerated hardware-software co-verification architecture built on the Zynq-7000 heterogeneous SoC, integrating an embedded RISC-V CPU with synthesized hardware logic in programmable fabric to jointly verify instruction-level semantics and RTL behavior. Our approach uniquely combines high-fidelity hardware emulation with near-real-time execution capability—achieving 5 MIPS throughput with <7% FPGA resource overhead. Compared to XSim, it delivers a 150× speedup; against Verilator, it is 35× faster. The framework supports agile ISA exploration, significantly reducing verification turnaround time and cost. It establishes a new, efficient, and scalable paradigm for RISC-V RTL-level verification.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: (Computational) Cognitive Architectures
• Search and Optimization: Sampling/Simulation-based Search

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Web Mining and Content Analysis: Web data generation and simulation

Abstract

Processor design and verification require a synergistic approach that combines instruction-level functional simulations with precise hardware emulations. The trade-off between speed and accuracy in the instruction set simulation poses a significant challenge to the efficiency of processor verification. By tapping the potentials of Field Programmable Gate Arrays (FPGAs), we propose an FPGA-assisted System-on-Chip (SoC) platform that facilitates cross-verification by the embedded CPU and the synthesized hardware in the programmable fabrics. This method accelerates the verification of the RISC-V Instruction Set Architecture (ISA) processor at a speed of 5 million instructions per second (MIPS), which is 150x faster than the vendor-specific tool (Xilinx XSim) and a 35x boost to the state-of-the-art open-source verification setup (Verilator). With less than 7% hardware occupation on Zynq 7000 FPGA, the proposed framework enables flexible verification with high time and cost efficiency for exploring RISC-V instruction set architectures.

Problem

• Balancing speed and accuracy in RISC-V processor verification
• Accelerating RTL verification using FPGA-assisted SoC platform
• Reducing hardware occupation while maintaining verification efficiency

Innovation

• FPGA-assisted SoC platform for verification
• 150x faster than Xilinx XSim
• Less than 7% FPGA hardware occupation