DreamRAM: A Fine-Grained Configurable Design Space Modeling Tool for Custom 3D Die-Stacked DRAM

2025-12-12

AI Summary

3D-stacked DRAM faces conflicting design requirements across power, performance, and area—making it challenging to simultaneously satisfy diverse application needs. Method: This paper proposes a fine-grained, customizable, configurable modeling framework tailored for domain-specific optimization. It introduces the novel Dataline-Over-MAT (DLOMAT) routing architecture and presents the first systematic, open physical design space model spanning multiple hierarchy levels—including memory array tiles (MATs), subarrays, banks, and inter-bank interconnects—enabling joint optimization of bandwidth, capacity, energy efficiency, latency, and die area. The framework integrates analytical circuit modeling, parameterized 3D interconnect modeling, and empirical calibration using HBM3/HBM2E measurement data, while enabling routing-aware, precise modeling of wire width, spacing, length, and capacitance. Results: Under equal-bandwidth, equal-capacity, and equal-power constraints, the framework achieves 66% higher bandwidth, 100% greater capacity, and 45% reduction in both energy-per-bit and power-per-bit.

Technology Category

• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Machine Learning: Hardware-aware ML
• Search and Optimization: Distributed Search

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs
• Search and Retrieval-Augmented AI: Vertical and domain-specific search

Abstract

3D die-stacked DRAM has emerged as a key technology for delivering high bandwidth and high density for applications such as high-performance computing, graphics, and machine learning. However, different applications place diverse and sometimes diverging demands on power, performance, and area that cannot be universally satisfied with fixed commodity DRAM designs. Die stacking creates the opportunity for a large DRAM design space through 3D integration and expanded total die area. To open and navigate this expansive design space of customized memory architectures that cater to application-specific needs, we introduce DreamRAM, a configurable bandwidth, capacity, energy, latency, and area modeling tool for custom 3D die-stacked DRAM designs. DreamRAM exposes fine-grained design customization parameters at the MAT, subarray, bank, and inter-bank levels, including extensions of partial page and subarray parallelism proposals found in the literature, to open a large previously-unexplored design space. DreamRAM analytically models wire pitch, width, length, capacitance, and scaling parameters to capture the performance tradeoffs of physical layout and routing design choices. Routing awareness enables DreamRAM to model a custom MAT-level routing scheme, Dataline-Over-MAT (DLOMAT), to facilitate better bandwidth tradeoffs. DreamRAM is calibrated and validated against published industry HBM3 and HBM2E designs. Within DreamRAM's rich design space, we identify designs that achieve each of 66% higher bandwidth, 100% higher capacity, and 45% lower power and energy per bit compared to the baseline design, each on an iso-bandwidth, iso-capacity, and iso-power basis.

Problem

• Modeling custom 3D die-stacked DRAM designs for diverse power, performance, and area demands.
• Exploring fine-grained design parameters at MAT, subarray, bank, and inter-bank levels.
• Enabling bandwidth, capacity, and energy tradeoffs through configurable analytical modeling.

Innovation

• DreamRAM enables fine-grained customization of 3D die-stacked DRAM designs
• It models physical layout and routing to optimize performance tradeoffs
• The tool introduces a custom MAT-level routing scheme called DLOMAT