Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing

2025-12-15

AI Summary

To address the slow software simulation and semantically impoverished random stimuli—leading to poor coverage convergence—in RISC-V processor verification, this paper proposes a novel verification framework integrating FPGA-based hardware acceleration with ISA-aware generative fuzzing. Our key contributions are: (1) LyraGen, the first domain-specific Transformer-based generative model explicitly encoding RISC-V instruction semantics, overcoming the semantic blindness inherent in conventional mutation-based fuzzing; and (2) a parallel differential execution architecture co-simulating the device under test (DUT) and a golden reference model, enabling hardware-accelerated, real-time coverage collection. Experimental results demonstrate that, compared to state-of-the-art software fuzzers, our approach achieves up to 1.27× higher coverage and accelerates end-to-end verification by 107×–3343×, significantly reducing convergence difficulty.

Technology Category

• Search and Optimization: Sampling/Simulation-based Search
• Machine Learning: Hardware-aware ML
• Computer Vision: Generative Adversarial Networks (GANs) for Vision

Application Category

• Search and Retrieval-Augmented AI: Retrieval-Augmented Generation (RAG) and multi-modal RAG
• Web Mining and Content Analysis: Web data generation and simulation
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs

Abstract

As processor designs grow more complex, verification remains bottlenecked by slow software simulation and low-quality random test stimuli. Recent research has applied software fuzzers to hardware verification, but these rely on semantically blind random mutations that may generate shallow, low-quality stimuli unable to explore complex behaviors. These limitations result in slow coverage convergence and prohibitively high verification costs. In this paper, we present Lyra, a heterogeneous RISC-V verification framework that addresses both challenges by pairing hardware-accelerated verification with an ISA-aware generative model. Lyra executes the DUT and reference model concurrently on an FPGA SoC, enabling high-throughput differential checking and hardware-level coverage collection. Instead of creating verification stimuli randomly or through simple mutations, we train a domain-specialized generative model, LyraGen, with inherent semantic awareness to generate high-quality, semantically rich instruction sequences. Empirical results show Lyra achieves up to $1.27 imes$ higher coverage and accelerates end-to-end verification by up to $107 imes$ to $3343 imes$ compared to state-of-the-art software fuzzers, while consistently demonstrating lower convergence difficulty.

Problem

• Addresses slow software simulation and low-quality random test stimuli in processor verification.
• Replaces semantically blind random mutations with an ISA-aware generative model for stimuli.
• Accelerates verification and improves coverage using hardware-accelerated FPGA-based differential checking.

Innovation

• Hardware-accelerated FPGA SoC for high-throughput differential checking
• ISA-aware generative model to produce semantically rich instruction sequences
• Domain-specialized fuzzing with inherent semantic awareness for coverage