HORCRUX: A Complete PQC RISC-V eXtension Architecture

2026-07-15

AI Summary

This work addresses the challenge of simultaneously achieving algorithmic agility, high performance, and low overhead for post-quantum cryptography (PQC) in resource-constrained embedded systems. The authors propose a compact RISC-V instruction set extension architecture that, for the first time, unifies support for all NIST-standardized PQC algorithms within a single hardware implementation. Integrated with a lightweight tightly coupled coprocessor, the design enhances both energy and area efficiency while maintaining backward compatibility with standard RISC-V cores. Implemented on a Zynq UltraScale+ FPGA, the architecture achieves speedups of up to 129×, 9×, and 27× for hash-based, lattice-based, and code-based schemes, respectively, with an overhead of less than 21k LUTs and 4.4k FFs. ASIC synthesis results in a 65nm process further confirm its superior energy efficiency.

Abstract

This work presents a compact RISC-V extension for Post-Quantum Cryptography (PQC) called HORCRUX, which provides a unified Instruction-Set Extension (ISE) supporting all NIST-approved PQC algorithms. HORCRUX addresses the difficult trade-off between crypto-agility, high performance, and low resource consumption in constrained environments, a balance typically missing in hardware extensions that focus on limited PQC subsets. By targeting shared kernels across ML-KEM, MLDSA, SLH-DSA, HQC, and Falcon, the extension introduces new RISC-V instructions executed by a resource-efficient, tightly coupled coprocessor. This architecture is specifically optimized for embedded systems with strict energy budgets and limited area. Experimental evaluation on a Zynq UltraScale+ FPGA demonstrates speedups of up to 129x for hash-based, 9x for lattice-based, and 27x for code-based schemes, while adding fewer than 21k LUTs and 4.4k FFs. ASIC results from postsynthesis characterization in 65 nm CMOS are also reported, alongside a rigorous power characterization to validate the architecture's energy efficiency. The extension's modular structure maintains backward compatibility with standard RISC-V cores, offering a scalable solution for deploying PQC on constrained embedded systems.

Problem

• Post-Quantum Cryptography
• RISC-V extension
• crypto-agility
• resource-constrained embedded systems
• hardware efficiency

Innovation

• Post-Quantum Cryptography
• RISC-V Extension
• Instruction-Set Architecture
• Hardware Acceleration
• Crypto-Agility