EXPLORE: Exploration with Guided Search for Analog Topology Generation using Language Models

2026-07-14

AI Summary

Automated generation of complex analog circuit topologies faces significant challenges due to the combinatorial explosion of the search space and severe data scarcity, rendering existing one-shot generation approaches inadequate for simultaneously achieving high accuracy and customization. This work proposes EXPLORE, a novel framework that uniquely integrates test-time structured search with language model decoding. Leveraging a pretrained Transformer to encode topological priors, EXPLORE employs simulator-guided Monte Carlo Tree Search (MCTS) to concentrate computational effort on critical design decisions and introduces a high-confidence token-skipping mechanism to allocate simulation resources efficiently. Evaluated on a six-component benchmark under a stringent 0.01 tolerance, the method substantially improves generation success rates from 12% (one-shot) and 33% (sample-and-filter) to 65%, while reducing mean squared error by over 20% under identical search budgets.

Abstract

Automating analog circuit topology design is essential to reduce the extensive manual effort required to meet increasingly diverse and customized application demands. Recent advances have applied sequence-to-sequence fine-tuning on pretrained language models to directly generate circuit topologies from user specifications in a single pass. However, these one-shot generation methods failed to generate complex circuits due to their exponentially growing search spaces and limited training datasets. In this paper, we present EXPLORE, a search-enhanced framework that integrates simulator-guided Monte Carlo Tree Search (MCTS) with transformer-based decoding to enable test-time scaling for analog topology generation. By leveraging language-model priors and bypassing high-confidence structural tokens, EXPLORE allocates expensive simulator budget primarily toward topology-altering decisions during search. On a 6-component benchmark at a tight tolerance of 0.01, EXPLORE raises the success rate from 12% for one-shot generation and 33% for a sampling-and-filter baseline to 65%, and lowers MSE by over 20% relative to sampling-and-filter under the same search budget. These results establish EXPLORE as the first framework to integrate structured test-time search with LM decoding for analog topology generation, and a practical step toward scaling LLM-driven design automation.

Problem

• analog circuit topology generation
• one-shot generation
• search space explosion
• limited training data
• design automation

Innovation

• Monte Carlo Tree Search
• language model decoding
• analog topology generation
• test-time scaling
• simulator-guided search