Algorithm-Driven On-Chip Integration for High Density and Low Cost

2025-12-10

AI Summary

To address layout inefficiency, communication redundancy, unmeasurable power consumption, and limited scalability in Multi-Project Wafer (MPW) platforms for large-scale chip education and research, this paper proposes a high-density, low-cost, and scalable on-chip shared architecture. Methodologically: (1) an algorithm-driven automated floorplanning framework maximizes die area utilization; (2) a novel lightweight interconnect and resource-sharing mechanism leverages site-gap regions, eliminating redundant dedicated I/O and memory macros; (3) modular power-domain partitioning and on-die power monitoring enable per-project power characterization. Experimental results demonstrate up to 13× reduction in die area compared to conventional physically co-located MPW implementations, significantly improving resource utilization and project throughput—without requiring expertise in low-power ASIC design.

Technology Category

• Machine Learning: Hardware-aware ML
• Multiagent Systems: Multiagent Planning
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Experiences and lessons learnt from Web-based algorithms and system deployments
• Security and Privacy: Large-scale security measurements
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs

Abstract

Growing interest in semiconductor workforce development has generated demand for platforms capable of supporting large numbers of independent hardware designs for research and training without imposing high per-project overhead. Traditional multi-project wafer (MPW) services based solely on physical co-placement have historically met this need, yet their scalability breaks down as project counts rise. Recent efforts towards scalable chip tapeouts mitigate these limitations by integrating many small designs within a shared die and attempt to amortize costly resources such as IO pads and memory macros. However, foundational principles for arranging, linking, and validating such densely integrated design sites have received limited systematic investigation. This work presents a new approach with three key techniques to address this gap. First, we establish a structured formulation of the design space that enables automated, algorithm-driven packing of many projects, replacing manual layout practices. Second, we introduce an architecture that exploits only the narrow-area regions between sites to deliver on off-chip communication and other shared needs. Third, we provide a practical approach for on-chip power domains enabling per-project power characterization at a standard laboratory bench and requiring no expertise in low-power ASIC design. Experimental results show that our approach achieves substantial area reductions of up to 13x over state-of-the-art physical-only aggregation methods, offering a scalable and cost-effective path forward for large-scale tapeout environments.

Problem

• Automated algorithm-driven packing of many projects
• Exploiting narrow-area regions for off-chip communication
• Providing on-chip power domains for per-project characterization

Innovation

• Algorithm-driven packing of multiple projects
• Narrow-area inter-site communication architecture
• On-chip power domains for lab characterization