Functional Reduction to Speed Up Bounded Model Checking

2025-12-06

AI Summary

Bounded Model Checking (BMC) suffers from deteriorating SAT-solving scalability as the unrolling depth increases. To address this, we propose FRAIG-BMC: a method that dynamically identifies and merges functionally equivalent nodes in transition relations during incremental unrolling, leveraging functional reduction and the Functionally Reduced And-Inverter Graph (FRAIG) representation. This enables online structural redundancy elimination and logic compression without requiring preprocessing, supporting real-time simplification of previously intractable large-scale circuits. Experimental evaluation across representative formal property verification (FPV) tasks—including sequential equivalence checking, partial register retention detection, and information-flow analysis—demonstrates that FRAIG-BMC achieves an average speedup of 2.3× over baseline BMC, with peak improvements up to 5.8×. The approach significantly enhances BMC efficiency while maintaining broad applicability and practical deployability.

Technology Category

• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories
• Knowledge Representation and Reasoning: Computational Complexity of Reasoning
• Reasoning under Uncertainty: Uncertainty Representations

Application Category

• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs
• Security and Privacy: Large-scale security measurements

Abstract

Bounded model checking (BMC) is a widely used technique for formal property verification (FPV), where the transition relation is repeatedly unrolled to increasing depths and encoded into Boolean satisfiability (SAT) queries. As the bound grows deeper, these SAT queries typically become more difficult to solve, posing scalability challenges. Howevefor, many FPV problems involve multiple copies of related circuits, creating opportunities to simplify the unrolled transition relation. Motivated by the functionally reduced and-inverter-graph (FRAIG) technique, we propose FRAIG-BMC, which incrementally identifies and merges functionally equivalent nodes during the unrolling process. By reducing redundancy, FRAIG-BMC improves the efficiency of SAT solving and accelerates property checking. Experiments demonstrate that FRAIG-BMC significantly speeds up BMC across a range of applications, including sequential equivalence checking, partial retention register detection, and information flow checking

Problem

• Speeds up bounded model checking by merging equivalent nodes
• Reduces redundancy in unrolled transition relations for efficiency
• Improves SAT solving performance in formal property verification

Innovation

• Incrementally merges functionally equivalent nodes during unrolling
• Reduces redundancy to improve SAT solving efficiency
• Applies FRAIG technique to accelerate bounded model checking