InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learning

2025-11-25

AI Summary

Traditional ATPG methods suffer from excessive runtime and limited fault coverage, while existing machine learning–based approaches—such as reinforcement learning (RL) with severe reward delay and graph neural networks (GNNs) with inadequate circuit representation capability—exhibit critical limitations. To address these challenges, this paper proposes an intelligent test vector generation framework integrating fanout-free region (FFR) partitioning, a dedicated graph neural network (QGNN), and RL. We innovatively design an FFR-driven circuit decomposition strategy to mitigate reward sparsity in RL training and develop a QGNN architecture specifically tailored for ATPG to enhance gate-level structural modeling. Experimental results demonstrate that our method reduces backtracking counts by 55.06% on average compared to conventional ATPG, and by 38.31% relative to state-of-the-art ML-based ATPG approaches, while achieving significantly higher fault coverage.

Technology Category

• Machine Learning: Graph-based Machine Learning
• Search and Optimization: Learning to Search
• Constraint Satisfaction and Optimization: Satisfiability

Application Category

• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications
• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking

Abstract

Automatic test pattern generation (ATPG) is a crucial process in integrated circuit (IC) design and testing, responsible for efficiently generating test patterns. As semiconductor technology progresses, traditional ATPG struggles with long execution times to achieve the expected fault coverage, which impacts the time-to-market of chips. Recent machine learning techniques, like reinforcement learning (RL) and graph neural networks (GNNs), show promise but face issues such as reward delay in RL models and inadequate circuit representation in GNN-based methods. In this paper, we propose InF-ATPG, an intelligent FFR-driven ATPG framework that overcomes these challenges by using advanced circuit representation to guide RL. By partitioning circuits into fanout-free regions (FFRs) and incorporating ATPG-specific features into a novel QGNN architecture, InF-ATPG enhances test pattern generation efficiency. Experimental results show InF-ATPG reduces backtracks by 55.06% on average compared to traditional methods and 38.31% compared to the machine learning approach, while also improving fault coverage.

Problem

• Improves test pattern generation efficiency in IC design
• Reduces execution time and backtracks for ATPG
• Enhances fault coverage with advanced circuit representation

Innovation

• FFR partitioning for circuit simplification
• QGNN with ATPG-specific feature integration
• Advanced circuit representation guiding reinforcement learning