🤖 AI Summary
Verifying the robustness of Binary Neural Networks (BNNs) is an NP-hard problem, rendering traditional exact methods intractable for high-dimensional settings. This work proposes the first formulation of this verification task as a Quadratic Unconstrained Binary Optimization (QUBO) problem and leverages an SRAM-based digital compute-in-memory (DCIM) Ising machine for efficient solution. By employing a voltage-controlled pseudo-read mechanism, the approach enables in-memory storage of QUBO coefficients and performs annealing iterations directly within the memory array. Notably, it rapidly identifies adversarial perturbations to falsify non-robustness without requiring global optimality. Compared to a CPU-based implementation, the proposed method achieves a 178× speedup in convergence and a 1,538× improvement in energy efficiency.
📝 Abstract
Verification of binary neural network (BNN) robustness is NP-hard, as it can be formulated as a combinatorial search for an adversarial perturbation that induces misclassification. Exact verification methods therefore scale poorly with problem dimension, motivating the use of hardware-accelerated heuristics and unconventional computing platforms, such as Ising solvers, that can efficiently explore complex energy landscapes and discover high-quality solutions. In this work, we reformulate BNN robustness verification as a quadratic unconstrained binary optimization (QUBO) problem and solve it using a digital compute-in-memory (DCIM) SRAM-based Ising machine. Instead of requiring globally optimal solutions, we exploit imperfect solutions produced by the DCIM Ising machine to extract adversarial perturbations and thereby demonstrate the non-robustness of the BNN. The proposed architecture stores quantized QUBO coefficients in approximately 9.1~Mb of SRAM and performs annealing in memory via voltage-controlled pseudo-read dynamics, enabling iterative updates with minimal data movement. Experimental projections indicate that the proposed approach achieves a $178\times$ acceleration in convergence rate and a $1538\times$ improvement in power efficiency relative to conventional CPU-based implementations.