ParaGate: Parasitic-Driven Domain Adaptation Transfer Learning for Netlist Performance Prediction

2025-11-28

AI Summary

In conventional EDA flows, layout-level timing and power metrics are only available post-placement-and-routing, severely hindering early-stage global optimization. This paper proposes a cross-stage performance prediction framework that enables high-accuracy, netlist-to-layout-level performance estimation for the first time. Our method introduces (1) a parasitic-aware two-stage transfer learning paradigm, and (2) tight coupling with industrial EDA tools for timing analysis, augmented by subgraph-level feature global calibration to mitigate inter-design distribution shift. By integrating neural networks, domain adaptation, and parasitic modeling, our approach achieves a substantial improvement in arrival time prediction accuracy on the openE906 benchmark—raising the R² score from 0.119 to 0.897—while requiring only minimal fine-tuning data for strong generalization across diverse designs. The framework delivers reliable performance feedback and optimization guidance directly to synthesis and placement stages, enabling earlier and more effective design space exploration.

Technology Category

• Machine Learning: Transfer, Domain Adaptation, Multi-Task Learning
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Game Theory and Economic Paradigms: Adversarial Learning

Application Category

• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics
• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization

Abstract

In traditional EDA flows, layout-level performance metrics are only obtainable after placement and routing, hindering global optimization at earlier stages. Although some neural-network-based solutions predict layout-level performance directly from netlists, they often face generalization challenges due to the black-box heuristics of commercial placement-and-routing tools, which create disparate data across designs. To this end, we propose ParaGate, a three-step cross-stage prediction framework that infers layout-level timing and power from netlists. First, we propose a two-phase transfer-learning approach to predict parasitic parameters, pre-training on mid-scale circuits and fine-tuning on larger ones to capture extreme conditions. Next, we rely on EDA tools for timing analysis, offloading the long-path numerical reasoning. Finally, ParaGate performs global calibration using subgraph features. Experiments show that ParaGate achieves strong generalization with minimal fine-tuning data: on openE906, its arrival-time R2 from 0.119 to 0.897. These results demonstrate that ParaGate could provide guidance for global optimization in the synthesis and placement stages.

Problem

• Predicts layout-level timing and power from netlists
• Addresses generalization issues in neural-network-based performance prediction
• Enables early-stage global optimization in EDA flows

Innovation

• Transfer learning predicts parasitic parameters from netlists
• EDA tools handle timing analysis for long-path reasoning
• Global calibration uses subgraph features for generalization