AssertMiner: Module-Level Spec Generation and Assertion Mining using Static Analysis Guided LLMs

2025-11-13

AI Summary

Existing assertion generation methods primarily target high-level specifications and struggle to detect microarchitectural module-level design errors. Method: This paper proposes AssertMiner, the first framework to leverage Abstract Syntax Tree (AST)-derived module call graphs, I/O tables, and data flow graphs as structured prompts—integrating static analysis with large language models (LLMs) to automatically mine and synthesize module-level assertions. By moving beyond natural-language-based specification inputs, AssertMiner enables precise, structural reasoning about low-level hardware logic. Contribution/Results: AssertMiner significantly improves assertion accuracy and coverage for detecting subtle microarchitectural bugs. Experimental evaluation shows it outperforms AssertLLM and Spec2Assertion in assertion quality; when integrated into verification flows, it increases structural coverage by 19.3% and fault detection rate by 32.7%.

Technology Category

• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories
• Knowledge Representation and Reasoning: Automated Reasoning and Theorem Proving
• Machine Learning: Hardware-aware ML

Application Category

• Web Mining and Content Analysis: Bridging structured and unstructured data
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics

Abstract

Assertion-based verification (ABV) is a key approach to checking whether a logic design complies with its architectural specifications. Existing assertion generation methods based on design specifications typically produce only top-level assertions, overlooking verification needs on the implementation details in the modules at the micro-architectural level, where design errors occur more frequently. To address this limitation, we present AssertMiner, a module-level assertion generation framework that leverages static information generated from abstract syntax tree (AST) to assist LLMs in mining assertions. Specifically, it performs AST-based structural extraction to derive the module call graph, I/O table, and dataflow graph, guiding the LLM to generate module-level specifications and mine module-level assertions. Our evaluation demonstrates that AssertMiner outperforms existing methods such as AssertLLM and Spec2Assertion in generating high-quality assertions for modules. When integrated with these methods, AssertMiner can enhance the structural coverage and significantly improve the error detection capability, enabling a more comprehensive and efficient verification process.

Problem

• Generating module-level assertions for micro-architectural verification in logic designs
• Overcoming limitations of top-level assertion methods that miss implementation details
• Improving error detection capability through static analysis guided assertion mining

Innovation

• Uses AST-based static analysis to guide LLMs
• Generates module-level specifications through structural extraction
• Mines assertions from call graphs and dataflow information