DS2SC-Agent: A Multi-Agent Automated Pipeline for Rapid Chiplet Model Generation
🤖 AI Summary
This work proposes DS2SC-Agent, the first end-to-end multi-agent automation framework for generating verified SystemC behavioral models of chiplet components directly from unstructured datasheets. Addressing the inefficiency and error-proneness of manual model creation and the unreliability of existing large language models in interpreting complex technical documentation, DS2SC-Agent orchestrates multiple agents to collaboratively parse raw chip specifications, synthesize SystemC code, construct testbenches, and perform closed-loop debugging. Experimental evaluation on representative analog, digital, and RF chiplets—including a limiting amplifier, an FFT module, and a power amplifier—demonstrates that the framework efficiently produces functionally correct models with minimal human intervention, validating its effectiveness and robustness in real-world engineering scenarios.
Application Category
📝 Abstract
Constructing behavioral-level chiplet models (e.g., SystemC) is crucial for early-stage heterogeneous architecture exploration. Traditional manual modeling is notoriously time-consuming and error-prone. Recently, Large Language Models (LLMs) have demonstrated immense potential in automating hardware code generation. However, existing LLM-assisted design frameworks predominantly target highly structured or well-defined design specifications. In practical engineering scenarios, raw datasheets typically encompass lengthy, complex, and highly unstructured information. Consequently, reliable code generation directly from these raw datasheets suffers from severe challenges, including context vanishing and logical hallucinations.To overcome this critical bottleneck, this paper proposes DS2SC-Agent(Datasheet-to-SystemC-Agent): the first end-to-end, fully automated generation pipeline that translates raw datasheets directly into SystemC chiplet models. This system establishes a highly efficient multi-agent collaborative framework. By decoupling the intricate modeling tasks, the proposed pipeline orchestrates a fully automated workflow encompassing unstructured long-document parsing, SystemC core code construction, testbench stimulus generation, and adaptive closed-loop debugging. We comprehensively evaluate the proposed framework on representative single-function chiplets across the analog, digital, and radio frequency (RF) domains--specifically, a Limiting Amplifier (LA), a Fast Fourier Transform (FFT) module, and a Power Amplifier (PA). The evaluation demonstrates that our pipeline seamlessly processes complex real-world datasheets to consistently generate functionally correct SystemC models. This provides a highly efficient and reliable paradigm for agile model library construction while drastically minimizing manual intervention.
Problem
Research questions and friction points this paper is trying to address.
Chiplet modeling
SystemC generation
Datasheet parsing
Automated hardware design
Unstructured document processing
Innovation
Methods, ideas, or system contributions that make the work stand out.
Multi-Agent System
Automated Hardware Generation
SystemC Modeling
Unstructured Datasheet Parsing
Chiplet Design Automation
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