BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement

2025-10-27

AI Summary

Chip placement critically impacts chip performance and design efficiency; however, existing black-box optimization (BBO) research suffers from inconsistent problem formulations and a lack of standardized evaluation benchmarks. To address this, we introduce the first dedicated BBO benchmark platform for chip placement, supporting diverse objective-driven formulations (e.g., wirelength-, timing-, and power-aware), modular algorithm integration, and plug-and-play evaluation. The platform encompasses representative BBO paradigms—including simulated annealing, evolutionary algorithms (EAs), Bayesian optimization, mask-guided search, and hyperparameter optimization. Experimental results demonstrate that EAs significantly outperform state-of-the-art methods in high-dimensional placement spaces, achieving new SOTA performance. This benchmark fills a critical gap in the field, enabling reproducible, comparable, and standardized evaluation of BBO techniques for chip design.

Technology Category

• Search and Optimization: Algorithm Configuration
• Constraint Satisfaction and Optimization: Solvers and Tools
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems

Application Category

• Economics, Online Markets and Human Computation: Research challenges in human and human-AI computation
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization

Abstract

Chip placement is a vital stage in modern chip design as it has a substantial impact on the subsequent processes and the overall quality of the final chip. The use of black-box optimization (BBO) for chip placement has a history of several decades. However, early efforts were limited by immature problem formulations and inefficient algorithm designs. Recent progress has shown the effectiveness and efficiency of BBO for chip placement, proving its potential to achieve state-of-the-art results. Despite these advancements, the field lacks a unified, BBO-specific benchmark for thoroughly assessing various problem formulations and BBO algorithms. To fill this gap, we propose BBOPlace-Bench, the first benchmark designed specifically for evaluating and developing BBO algorithms for chip placement tasks. It integrates three problem formulations of BBO for chip placement, and offers a modular, decoupled, and flexible framework that enables users to seamlessly implement, test, and compare their own algorithms. BBOPlace-Bench integrates a wide variety of existing BBO algorithms, including simulated annealing (SA), evolutionary algorithms (EAs), and Bayesian optimization (BO). Experimental results show that the problem formulations of mask-guided optimization and hyperparameter optimization exhibit superior performance than the sequence pair problem formulation, while EAs demonstrate better overall performance than SA and BO, especially in high-dimensional search spaces, and also achieve state-of-the-art performance compared to the mainstream chip placement methods. BBOPlace-Bench not only facilitates the development of efficient BBO-driven solutions for chip placement but also broadens the practical application scenarios (which are urgently needed) for the BBO community. The code of BBOPlace-Bench is available at https://github.com/lamda-bbo/BBOPlace-Bench.

Problem

• Lacks unified benchmark for black-box optimization in chip placement
• Evaluates three problem formulations and various BBO algorithms
• Facilitates development of efficient BBO-driven chip placement solutions

Innovation

• First benchmark for black-box optimization in chip placement
• Integrates three problem formulations and modular framework
• Evaluates algorithms including evolutionary and Bayesian optimization