Optimization and Benchmarking of Monolithically Stackable Gain Cell Memory for Last-Level Cache

2025-03-08

AI Summary

In the post-Moore era, last-level caches (LLCs) face escalating challenges in achieving high density, low static power, and high bandwidth simultaneously. Method: This paper proposes a monolithic 3D (M3D)-integrated, back-end-of-line (BEOL)-compatible amorphous oxide semiconductor (AOS) two-transistor gain-cell (2T-GC) memory architecture for LLCs. It presents the first systematic optimization of AOS 2T-GC for LLC applications and introduces NS-Cache—a cycle-accurate modeling framework tightly coupled with Gem5—to enable fair, cross-node (7 nm/3 nm) and cross-technology (HD-SRAM/MRAM/eDRAM) evaluation. Results: At the 3 nm node, the proposed design achieves 3.2× higher memory density and 41% lower access energy versus HD-SRAM, while reducing standby leakage to second-scale retention. This work validates M3D-integrated AOS 2T-GC as a viable path toward ultra-high-capacity, ultra-low-power LLCs, offering a promising alternative to overcome SRAM scaling limitations.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Distributed Search
• Cognitive Modeling & Cognitive Systems: Agent Architectures

Application Category

• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs
• Economics, Online Markets and Human Computation: Architectures and workflows that use LLMs for crowd work
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs

Abstract

The Last Level Cache (LLC) is the processor's critical bridge between on-chip and off-chip memory levels - optimized for high density, high bandwidth, and low operation energy. To date, high-density (HD) SRAM has been the conventional device of choice; however, with the slowing of transistor scaling, as reflected in the industry's almost identical HD SRAM cell size from 5 nm to 3 nm, alternative solutions such as 3D stacking with advanced packaging like hybrid bonding are pursued (as demonstrated in AMD's V-cache). Escalating data demands necessitate ultra-large on-chip caches to decrease costly off-chip memory movement, pushing the exploration of device technology toward monolithic 3D (M3D) integration where transistors can be stacked in the back-end-of-line (BEOL) at the interconnect level. M3D integration requires fabrication techniques compatible with a low thermal budget (<400 degC). Among promising BEOL device candidates are amorphous oxide semiconductor (AOS) transistors, particularly desirable for their ultra-low leakage (seconds) when used in a gain-cell configuration. This paper examines device, circuit, and system-level tradeoffs when optimizing BEOL-compatible AOS-based 2-transistor gain cell (2T-GC) for LLC. A cache early-exploration tool, NS-Cache, is developed to model caches in advanced 7 and 3 nm nodes and is integrated with the Gem5 simulator to systematically benchmark the impact of the newfound density/performance when compared to HD-SRAM, MRAM, and 1T1C eDRAM alternatives for LLC.

Problem

• Optimizing monolithically stackable gain cell memory for Last-Level Cache.
• Exploring 3D stacking with advanced packaging to enhance cache density.
• Benchmarking AOS-based 2T-GC against HD-SRAM, MRAM, and 1T1C eDRAM.

Innovation

• Monolithic 3D integration for high-density cache
• Amorphous oxide semiconductor transistors for low leakage
• NS-Cache tool for advanced node cache modeling