Real-time CARFAC Cochlea Model Acceleration on FPGA for Underwater Acoustic Sensing Systems
To address the real-time performance and energy-efficiency bottlenecks of the CARFAC cochlear model in underwater acoustic sensing, this work proposes a software-hardware co-design acceleration framework on the AMD Kria KV260 platform. The approach employs Rust for a low-overhead control layer and leverages FPGA acceleration with time-division multiplexing, deep pipelining, and a division-free CARFAC core implementation. The system achieves real-time, synchronized preprocessing for up to 64 hydrophones at 256 kHz sampling rate. It consumes only 13.5% of the FPGA’s logic resources and operates at just 3.11 W total board power, while preserving biological fidelity. This is the first demonstration of full-rate, high-channel-count CARFAC deployment on an embedded FPGA platform. The architecture delivers significantly improved throughput and energy efficiency, establishing a scalable foundation for edge-intelligent, biomimetic underwater auditory processing.