Selected work

Representative Papers

Detecting Architectural Drift in Safety-Critical Firmware through Runtime Trace Analysis

Jul 03, 2026

This work addresses the challenge of detecting architectural drift—discrepancies between design-time architecture and runtime behavior—in long-lived embedded firmware. The authors propose a practical, hardware-assisted detection approach that captures runtime execution traces, abstracts them into inter-component message interaction sequences, and performs deterministic comparison against design-phase UML sequence diagrams to precisely identify confirmed, missing, extraneous, or inverted behavioral deviations. To facilitate expert review, the method further leverages a constrained large language model to generate human-readable explanatory reports. Integrating runtime trace analysis, deterministic architectural conformance checking, and constraint-guided LLM-based explanation generation for the first time, the approach demonstrates high agreement with expert annotations across 26 industrial cases, substantially reducing manual analysis effort while effectively supporting ISO 26262 safety documentation requirements.

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Understanding Inference Scaling for LLMs: Bottlenecks, Trade-offs, and Performance Principles

May 19, 2026

This study addresses the limitations of dense large language models in long-chain reasoning, where fragmented KV caches and parallelization inefficiencies undermine traditional prefill extension strategies. Through systematic evaluation of dense and Mixture-of-Experts models ranging from 8B to 671B parameters on GPU clusters, the work uncovers critical performance bottlenecks: a sharp drop in data parallelism efficiency due to cache fragmentation, a nonlinear scaling inflection point in tensor parallelism around 32B parameters, and fundamental differences between sparse and dense architectures in interconnect bandwidth utilization and routing latency. Guided by extensive empirical analysis, the authors propose an architecture decision framework tailored to the “inference cliff” phenomenon, establishing design principles for next-generation LLM inference infrastructure that substantially improve resource utilization and throughput efficiency.

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Performance and Energy Benefits of MRDIMMs

May 04, 2026

This work presents the first comprehensive system-level evaluation of Multiplexed Rank DIMM (MRDIMM) architecture in high-end production servers, addressing the memory bandwidth bottleneck inherent in conventional memory systems without increasing DRAM frequency. By circumventing the power and energy-efficiency challenges associated with higher DRAM clock rates, MRDIMM delivers substantial improvements in both bandwidth and latency. Experimental results demonstrate that, at identical power consumption, MRDIMM achieves a 41% increase in memory bandwidth compared to RDIMM, yielding 27–41% performance gains for bandwidth-sensitive workloads and reducing memory access latency by hundreds of nanoseconds. Furthermore, memory-intensive applications benefit from up to 30% reduction in server energy consumption, underscoring MRDIMM’s compelling advantages in both performance and energy efficiency.

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Inferring Equivalence Classes from Legacy Undocumented Embedded Binaries for ISO 26262-Compliant Testing

Apr 24, 2026

This work addresses the challenge of applying equivalence class partitioning—a testing requirement under ISO 26262—to legacy embedded firmware in the absence of complete specification documents. The authors propose a binary-level method that automatically infers output-oriented equivalence classes by reconstructing control flow and performing guided symbolic execution to analyze function behavior. Execution paths are clustered based on observable outputs, such as return values and output parameters, and the resulting equivalence classes are represented in a human-readable form to support test design. To the best of the authors’ knowledge, this is the first approach capable of inferring equivalence classes directly from binaries without source code or documentation for safety-critical embedded software. Industrial case studies demonstrate that the inferred classes align closely with expert expectations and offer both high readability and practical utility, effectively aiding functional comprehension and compliance testing of legacy firmware.

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Co-Design of Memory-Storage Systems for Workload Awareness with Interpretable Models

Mar 16, 2026

This work proposes an interpretable machine learning–based cross-layer co-design methodology to address the challenge of jointly optimizing reliability and performance in high-density solid-state storage systems. By constructing the first representation learning framework that unifies NAND flash error management with diverse real-world and synthetic workloads—including JEDEC and YCSB benchmarks—and integrating it with an abstracted Flash Translation Layer model, the study systematically analyzes the interaction mechanisms between memory components and firmware algorithms. Extensive experiments across thousands of multi-generation datacenter SSDs demonstrate that the proposed approach significantly enhances storage architecture design efficiency, enables data-driven continuous evolution, and achieves synergistic optimization of both reliability and performance under realistic and synthetic workloads.

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Recent publications

Latest Papers

Detecting Architectural Drift in Safety-Critical Firmware through Runtime Trace Analysis

Jul 03, 2026

This work addresses the challenge of detecting architectural drift—discrepancies between design-time architecture and runtime behavior—in long-lived embedded firmware. The authors propose a practical, hardware-assisted detection approach that captures runtime execution traces, abstracts them into inter-component message interaction sequences, and performs deterministic comparison against design-phase UML sequence diagrams to precisely identify confirmed, missing, extraneous, or inverted behavioral deviations. To facilitate expert review, the method further leverages a constrained large language model to generate human-readable explanatory reports. Integrating runtime trace analysis, deterministic architectural conformance checking, and constraint-guided LLM-based explanation generation for the first time, the approach demonstrates high agreement with expert annotations across 26 industrial cases, substantially reducing manual analysis effort while effectively supporting ISO 26262 safety documentation requirements.

0 citationsRead paper

Understanding Inference Scaling for LLMs: Bottlenecks, Trade-offs, and Performance Principles

May 19, 2026

This study addresses the limitations of dense large language models in long-chain reasoning, where fragmented KV caches and parallelization inefficiencies undermine traditional prefill extension strategies. Through systematic evaluation of dense and Mixture-of-Experts models ranging from 8B to 671B parameters on GPU clusters, the work uncovers critical performance bottlenecks: a sharp drop in data parallelism efficiency due to cache fragmentation, a nonlinear scaling inflection point in tensor parallelism around 32B parameters, and fundamental differences between sparse and dense architectures in interconnect bandwidth utilization and routing latency. Guided by extensive empirical analysis, the authors propose an architecture decision framework tailored to the “inference cliff” phenomenon, establishing design principles for next-generation LLM inference infrastructure that substantially improve resource utilization and throughput efficiency.

0 citationsRead paper

Performance and Energy Benefits of MRDIMMs

May 04, 2026

This work presents the first comprehensive system-level evaluation of Multiplexed Rank DIMM (MRDIMM) architecture in high-end production servers, addressing the memory bandwidth bottleneck inherent in conventional memory systems without increasing DRAM frequency. By circumventing the power and energy-efficiency challenges associated with higher DRAM clock rates, MRDIMM delivers substantial improvements in both bandwidth and latency. Experimental results demonstrate that, at identical power consumption, MRDIMM achieves a 41% increase in memory bandwidth compared to RDIMM, yielding 27–41% performance gains for bandwidth-sensitive workloads and reducing memory access latency by hundreds of nanoseconds. Furthermore, memory-intensive applications benefit from up to 30% reduction in server energy consumption, underscoring MRDIMM’s compelling advantages in both performance and energy efficiency.

0 citationsRead paper

Inferring Equivalence Classes from Legacy Undocumented Embedded Binaries for ISO 26262-Compliant Testing

Apr 24, 2026

This work addresses the challenge of applying equivalence class partitioning—a testing requirement under ISO 26262—to legacy embedded firmware in the absence of complete specification documents. The authors propose a binary-level method that automatically infers output-oriented equivalence classes by reconstructing control flow and performing guided symbolic execution to analyze function behavior. Execution paths are clustered based on observable outputs, such as return values and output parameters, and the resulting equivalence classes are represented in a human-readable form to support test design. To the best of the authors’ knowledge, this is the first approach capable of inferring equivalence classes directly from binaries without source code or documentation for safety-critical embedded software. Industrial case studies demonstrate that the inferred classes align closely with expert expectations and offer both high readability and practical utility, effectively aiding functional comprehension and compliance testing of legacy firmware.

0 citationsRead paper

Co-Design of Memory-Storage Systems for Workload Awareness with Interpretable Models

Mar 16, 2026

This work proposes an interpretable machine learning–based cross-layer co-design methodology to address the challenge of jointly optimizing reliability and performance in high-density solid-state storage systems. By constructing the first representation learning framework that unifies NAND flash error management with diverse real-world and synthetic workloads—including JEDEC and YCSB benchmarks—and integrating it with an abstracted Flash Translation Layer model, the study systematically analyzes the interaction mechanisms between memory components and firmware algorithms. Extensive experiments across thousands of multi-generation datacenter SSDs demonstrate that the proposed approach significantly enhances storage architecture design efficiency, enables data-driven continuous evolution, and achieves synergistic optimization of both reliability and performance under realistic and synthetic workloads.

0 citationsRead paper