Selected work

Representative Papers

Information Flow Paths from RTL Traces

Jun 11, 2026

This work proposes a novel approach to hardware security verification by automatically constructing end-to-end information flow paths from register transfer level (RTL) trace data. Unlike conventional information flow analyses that merely detect whether data flows between registers, the proposed method reconstructs complete propagation pathways of sensitive information at the RTL trace level for the first time. By integrating information flow tracking with specification mining techniques, the framework automatically generates and verifies security properties. This paradigm overcomes the limitations of pairwise flow detection, substantially enhancing the automation, precision in violation detection, and efficiency of system-wide security evaluation in hardware designs.

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RTL-Arrow: Hardware-to-Cloud Bridge

Jun 11, 2026

This work addresses the inefficiency of manual VCD file analysis in hardware security research, where practitioners often laboriously inspect waveform traces to identify software-hardware interface vulnerabilities. To overcome this bottleneck, the paper introduces RTL-Arrow, a novel framework that automatically transforms VCD execution traces—generated from hardware simulation—into cloud-ready, structured data frames compatible with modern data science workflows. RTL-Arrow integrates VCD parsing, structured data frame construction, and cloud-native format encapsulation, complemented by an automated compilation pipeline that produces a high-performance toolchain. Released as an open-source library, RTL-Arrow substantially lowers the barrier to hardware-software co-verification, significantly enhancing the efficiency and scalability of cross-layer vulnerability detection and analysis.

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Enhancing Software Testing Education: Understanding Where Students Struggle

Oct 01, 2025

Computer science students frequently exhibit persistent misconceptions about core testing concepts—particularly decision coverage and exception handling—leading to superficial test modifications that fail to improve code coverage. This study employs an automated testing feedback tool to systematically analyze multi-version student submissions and corresponding coverage changes, providing the first empirical identification of these two conceptual misunderstandings and their strong association with ineffective modification behaviors. Results show that over 70% of student test modifications yield no statistically significant coverage improvement, with errors predominantly occurring in branch decision logic and omitted exception-handling paths. The work reveals critical cognitive bottlenecks in testing education and delivers empirically grounded, actionable insights for designing targeted pedagogical interventions and intelligent, context-aware feedback tools.

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"vcd2df"-- Leveraging Data Science Insights for Hardware Security Research

May 09, 2025

This work addresses the disconnect between RTL simulation traces (in VCD format) and modern data science tools in hardware security analysis. Methodologically, we introduce a lightweight VCD-to-DataFrame library that enables low-overhead mapping of VCD files to Python/R DataFrames, and— for the first time—integrate Apache Spark DataFrames into hardware security analysis to support distributed, parallel trace processing. Our contributions are threefold: (1) We establish the first technical pathway enabling seamless integration of hardware simulation traces into the data science stack; (2) We propose a DataFrame-based abstraction for generic hardware trace analysis, supporting sub-second trace loading and interactive exploration; and (3) We empirically validate the feasibility and scalability of this paradigm on side-channel feature extraction and anomaly behavior detection tasks, significantly lowering the barrier to entry for open-source hardware security research.

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"Test, Build, Deploy"- A CI/CD Framework for Open-Source Hardware Designs

Mar 24, 2025

To address the lack of systematic continuous verification and secure release mechanisms in open-source hardware design, this paper pioneers the systematic adaptation of software CI/CD paradigms to the hardware domain, proposing a general-purpose framework for automatic hardware specification mining and continuous deployment. Methodologically, it integrates HDL static analysis, machine learning–driven specification inference, formal verification, and cloud-native automated pipelines, implemented in the prototype system Myrtha. Key contributions include: (1) the first CI/CD architecture supporting continuous hardware specification generation, verification, and release; (2) a scalable, automated specification mining mechanism that overcomes traditional manual modeling bottlenecks; and (3) substantial improvements in quality assurance, experimental reproducibility, and cross-team collaboration efficiency for open-source hardware development.

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Recent publications

Latest Papers

Information Flow Paths from RTL Traces

Jun 11, 2026

This work proposes a novel approach to hardware security verification by automatically constructing end-to-end information flow paths from register transfer level (RTL) trace data. Unlike conventional information flow analyses that merely detect whether data flows between registers, the proposed method reconstructs complete propagation pathways of sensitive information at the RTL trace level for the first time. By integrating information flow tracking with specification mining techniques, the framework automatically generates and verifies security properties. This paradigm overcomes the limitations of pairwise flow detection, substantially enhancing the automation, precision in violation detection, and efficiency of system-wide security evaluation in hardware designs.

0 citationsRead paper

RTL-Arrow: Hardware-to-Cloud Bridge

Jun 11, 2026

This work addresses the inefficiency of manual VCD file analysis in hardware security research, where practitioners often laboriously inspect waveform traces to identify software-hardware interface vulnerabilities. To overcome this bottleneck, the paper introduces RTL-Arrow, a novel framework that automatically transforms VCD execution traces—generated from hardware simulation—into cloud-ready, structured data frames compatible with modern data science workflows. RTL-Arrow integrates VCD parsing, structured data frame construction, and cloud-native format encapsulation, complemented by an automated compilation pipeline that produces a high-performance toolchain. Released as an open-source library, RTL-Arrow substantially lowers the barrier to hardware-software co-verification, significantly enhancing the efficiency and scalability of cross-layer vulnerability detection and analysis.

0 citationsRead paper

Enhancing Software Testing Education: Understanding Where Students Struggle

Oct 01, 2025

Computer science students frequently exhibit persistent misconceptions about core testing concepts—particularly decision coverage and exception handling—leading to superficial test modifications that fail to improve code coverage. This study employs an automated testing feedback tool to systematically analyze multi-version student submissions and corresponding coverage changes, providing the first empirical identification of these two conceptual misunderstandings and their strong association with ineffective modification behaviors. Results show that over 70% of student test modifications yield no statistically significant coverage improvement, with errors predominantly occurring in branch decision logic and omitted exception-handling paths. The work reveals critical cognitive bottlenecks in testing education and delivers empirically grounded, actionable insights for designing targeted pedagogical interventions and intelligent, context-aware feedback tools.

0 citationsRead paper

"vcd2df"-- Leveraging Data Science Insights for Hardware Security Research

May 09, 2025

This work addresses the disconnect between RTL simulation traces (in VCD format) and modern data science tools in hardware security analysis. Methodologically, we introduce a lightweight VCD-to-DataFrame library that enables low-overhead mapping of VCD files to Python/R DataFrames, and— for the first time—integrate Apache Spark DataFrames into hardware security analysis to support distributed, parallel trace processing. Our contributions are threefold: (1) We establish the first technical pathway enabling seamless integration of hardware simulation traces into the data science stack; (2) We propose a DataFrame-based abstraction for generic hardware trace analysis, supporting sub-second trace loading and interactive exploration; and (3) We empirically validate the feasibility and scalability of this paradigm on side-channel feature extraction and anomaly behavior detection tasks, significantly lowering the barrier to entry for open-source hardware security research.

0 citationsRead paper

"Test, Build, Deploy"- A CI/CD Framework for Open-Source Hardware Designs

Mar 24, 2025

To address the lack of systematic continuous verification and secure release mechanisms in open-source hardware design, this paper pioneers the systematic adaptation of software CI/CD paradigms to the hardware domain, proposing a general-purpose framework for automatic hardware specification mining and continuous deployment. Methodologically, it integrates HDL static analysis, machine learning–driven specification inference, formal verification, and cloud-native automated pipelines, implemented in the prototype system Myrtha. Key contributions include: (1) the first CI/CD architecture supporting continuous hardware specification generation, verification, and release; (2) a scalable, automated specification mining mechanism that overcomes traditional manual modeling bottlenecks; and (3) substantial improvements in quality assurance, experimental reproducibility, and cross-team collaboration efficiency for open-source hardware development.

0 citationsRead paper