data plane development kit

To address high latency and low throughput in Linux’s conventional TCP/IP stack—caused by kernel processing overhead, context switches, and data copying—on 100 Gbps+ high-end NICs, this paper proposes a microkernel-inspired network stack redesign. The approach integrates DPDK-based hardware acceleration with a user-space TCP/IP stack, achieving zero-copy I/O, kernel bypass, and a streamlined data path while maintaining full backward compatibility with unmodified applications. Its core innovation lies in migrating critical networking functions to user space, while retaining kernel responsibilities for security, reliability, and generic device management. Experimental evaluation on mainstream x86 servers demonstrates that the design reduces end-to-end latency by 62%, cuts CPU utilization by 47%, and improves throughput by 2.3× compared to the standard kernel stack. The solution is production-ready, offering a high-performance, compatible, and deployable network infrastructure for modern distributed computing systems.

Existing user-space network stacks suffer from poor portability and deployment challenges due to overreliance on vendor-specific vNIC hardware features (e.g., flow classification, RSS reconfiguration) and rigid execution models. This work introduces Machnet, a lightweight user-space network stack designed for public cloud VMs. Machnet proposes a novel “least-common-denominator” virtual NIC abstraction—defining a minimal, cross-vendor-compatible set of primitives—and adopts a microkernel architecture instead of a library OS to balance flexibility with low inter-process communication overhead. Leveraging zero-copy I/O and a streamlined protocol stack, it achieves throughput and latency comparable to high-end, hardware-optimized stacks—even on commodity vNICs. Evaluated across major public clouds, Machnet demonstrates broad compatibility, simplified deployment, and enhanced developer ergonomics. It establishes a new paradigm for practical, portable user-space networking in heterogeneous cloud environments.

This work addresses the challenge in network link emulation where variable delay often introduces excessive latency or packet reordering. To mitigate these issues, the authors propose an adaptive delay correlation mechanism based on DPDK that dynamically adjusts inter-packet delays. The approach effectively avoids both over-delay and packet reordering while simultaneously supporting bandwidth limitation, traffic shaping, rate limiting, and two distinct packet loss models. Experimental results demonstrate that the system achieves zero-packet-loss throughput of 95 Gbit/s under constant delay and 85 Gbit/s with 3 ms jitter on hardware, significantly outperforming NetEm and MoonEm. The study also provides practical configuration guidelines for the critical half-life parameter governing the adaptive behavior.

This work addresses the performance limitations of DPDK memory pools in multicore high-speed packet processing, which stem from lock contention, cache coherence overhead, TLB pressure, and the complexity and fragmentation associated with explicit huge page configuration. To overcome these challenges, the authors propose a novel lock-free memory pool architecture based on C++ templates that, for the first time, integrates transparent huge page auto-compaction with a fully lock-free design. This approach automatically leverages the benefits of huge pages without manual configuration. Locality is further enhanced through per-core local caches, atomic stacks, NUMA node binding, and CPU affinity. Experimental results on a 100 Gbps platform demonstrate up to a 28% improvement in throughput and a 41% reduction in TLB misses compared to the standard DPDK memory pool.

Datacenter networks (DCNs) face challenges from switch chip capacity constraints, buffer-induced latency, and control-plane complexity. Method: This paper proposes Fastpod—a zero-buffer architecture enabling collision-free, deterministic intra-Pod transmission under tight time synchronization. It employs centralized fine-grained packet scheduling and a coordination-free control plane to ensure scalability; introduces optimistic forward transmission to mitigate centralized control latency; and offloads intelligence to the network edge, establishing a “simplified core, enhanced edge” paradigm. Contribution/Results: Simulation results demonstrate 100% collision-free intra-Pod delivery, end-to-end latency competitive with conventional buffered DCNs, and seamless integration with buffered backbone layers. To our knowledge, Fastpod is the first architecture achieving zero-buffer, collision-free operation at the Pod level, thereby extending the design frontier of deterministic networking.

SmartNIC Data Processing Units (DPUs) offer a promising solution for saving high-end CPU resources by offloading tasks to programmable cores near the network interface. In this work, we explore the feasibility of SmartNIC DPUs in supporting an asynchronous communication model called "fire-and-forget", particularly its core message routing service. We design a communication offloading engine called Buddy that decouples communication tasks from the application process. Buddy runs flexibly on SmartNIC DPUs such as the Nvidia BlueField-3 DPU and generic x86 CPUs. Our evaluation results in five applications identify the memory-to-communication ratio as a key predictor of the offloading performance. Host-dominated workloads, such as Quicksilver and Sparse Matrix Transpose, achieved up to 1.55x speedup with communication offloaded to the DPU. We further identify a 625x increase in DRAM traffic due to the absence of Direct Cache Access support on the DPU, highlighting a critical need in future SmartNIC designs.

Existing transport-layer hardware struggles to flexibly support the evolution of new protocols due to rigid protocol logic or reliance on protocol-specific assumptions. This work proposes PITA, a novel architecture that reconfigures core components—such as scheduling, packet generation, and data reassembly—through a unified event–state–instruction abstraction model, enabling a protocol-agnostic and line-rate programmable transport-layer datapath. By eliminating protocol-specific assumptions, PITA efficiently supports semantically diverse protocols, including TCP and RoCE, on a single FPGA (Alveo U250) while fully preserving their end-to-end behavioral differences. Experimental results demonstrate that the system meets timing constraints at 250 MHz with low hardware overhead and excellent performance.

This work addresses the performance bottleneck in traditional databases caused by reliance on the kernel TCP stack, which becomes a CPU-intensive black box in high-speed cloud networks. To overcome this limitation, the authors propose a dual-channel networking paradigm that decouples database communication into a high-performance data channel based on user-space UDP and a reliable control channel leveraging kernel TCP. By co-designing the database with modern NIC hardware features, this approach simultaneously achieves low latency, high throughput, and strong reliability. Empirical results demonstrate that the system saturates a 200 Gbit/s network link using only three CPU cores during distributed shuffle operations and enables a replicated key-value store to process millions of messages per second.