cache contention analysis

This paper addresses the long-standing challenge of quantitatively analyzing non-LRU cache replacement policies—such as FIFO and MRU—under arbitrary associativity and microarchitectural timing anomalies. We propose the first unified analytical framework for this problem. Methodologically, we introduce the novel concept of *block competitiveness*, enabling systematic transfer of LRU persistence analysis to non-LRU policies, and integrate worst-case execution time (WCET) analysis techniques to overcome the infeasibility of conventional approaches under timing anomalies. Our contributions are threefold: (1) the first rigorous, block-level competitiveness modeling for FIFO and MRU; (2) high-precision quantification of cache behavior across arbitrary cache ways and timing-anomalous microarchitectures; and (3) empirical validation on the TACLeBench benchmark suite, demonstrating accuracy approaching that of LRU-based analysis while ensuring both theoretical soundness and engineering deployability.

This work addresses key challenges in Profile-Guided Optimization (PGO): high sampling overhead, poor adaptability to dynamic inputs, and weak cross-architecture portability. We systematically survey and restructure the PGO technical landscape, proposing the first multi-dimensional classification framework for PGO—explicitly identifying three core research directions: low-overhead profiling, dynamic workload adaptation, and cross-architecture profile migration. Our approach unifies instrumentation- and sampling-based analysis, enabling compiler- and linker-time collaborative optimization in GCC and LLVM across heterogeneous targets including x86 and ARM. Empirical evaluation on standard benchmarks demonstrates an average performance improvement of 12.3%, while reducing profiling overhead to under 0.8%. These results significantly enhance the industrial deployability and generalization capability of PGO.

Traditional approaches struggle to provide deep visibility into the internal behavior of the gem5 simulator. This work proposes a non-intrusive, lightweight runtime call-stack analysis framework that, for the first time, treats the simulator’s own execution path as a novel lens for understanding simulated system behavior. Built upon the Linux perf_event interface, the framework enables parallel sampling, real-time symbol resolution, and hierarchical call-tree aggregation, with support for component-level customizable analysis. Experimental results demonstrate its effectiveness in uncovering performance bottlenecks in TimingSimpleCPU and identifying deadlock and livelock issues within the Ruby memory system—capturing critical behavioral characteristics that conventional statistical methods fail to detect.

Accurate characterization of microarchitectural behavior using hardware performance counters is hindered by ambiguous specifications, opaque designs, and multiplexing-induced noise, impeding experts’ ability to validate hypotheses. This work proposes CounterPoint, a framework that for the first time systematically integrates formal microarchitectural models—represented as μ-path decision diagrams—with noisy performance counter data. By comparing multidimensional confidence regions derived from the model against observed hardware events, CounterPoint automatically detects inconsistencies and pinpoints potential undocumented microarchitectural features. Applied to Intel Haswell’s memory management unit, the approach successfully uncovers several previously undisclosed mechanisms, including a load-store queue–side TLB prefetcher, a mergeable page table walker, and an abortable page table walk capability.

This paper addresses the static verification of data races in concurrent programs. We propose an abstraction-interpreter-based, summary-driven analysis method. Our core innovation is a thread-modularized local trace semantics that abstracts program execution histories into multidimensional summaries—comprising lock sets, thread identifiers, and join relations—and formally encodes conflict exclusion conditions to achieve high-precision race detection. Compared to conventional lock-set analysis, our approach significantly improves concurrency sensitivity and reasoning capability. Experimental evaluation on the SV-COMP benchmark demonstrates that integrating these multidimensional summaries increases the number of correctly solved verification tasks by over fivefold, thereby validating both the effectiveness and practicality of the method.

This work addresses the limitations of traditional hardware prefetchers, which rely on manual analysis of program traces and struggle to handle performance anomalies in real-world workloads. The authors propose a performance-anomaly-driven automated design methodology that employs an intelligent agent to diagnose prefetching failures, automatically synthesize a Mixture-of-Prefetchers (MoP), and continuously refine it through simulation. This approach represents the first practical, agent-driven framework capable of generating synthesizable RTL for prefetchers, outperforming state-of-the-art handcrafted designs on previously unseen workloads. Evaluated on SPEC CPU2006/2017, MoP achieves a 61.1% geometric mean IPC improvement over no prefetching and surpasses Alecto, Berti, and Pythia by 14.5%–23.6%. Its RTL implementation in a 6nm process occupies only 110KB of storage and 0.0347mm² of silicon area.

This work addresses the subtle microarchitectural performance inefficiencies often introduced by modern compiler optimizations, which can lead to significant yet overlooked performance losses. The authors propose a top-down differential analysis methodology that systematically identifies and categorizes the root causes of such optimization defects by integrating fine-grained microarchitectural performance counter sampling with cross-compiler (GCC/Clang) binary comparisons. Innovatively combining top-down microarchitectural analysis with differential testing, the approach further introduces a portable binary patching framework to precisely locate and rectify inefficient code segments. Empirical evaluation demonstrates that the method effectively uncovers substantial but commonly neglected performance discrepancies between GCC and Clang and successfully recovers performance through targeted binary patches.

This work addresses the phase-sensitive interplay between prefetching and replacement policies in modern processors, where static configurations often fail to sustain optimal performance due to dynamic workload behavior. For the first time, it reveals the strong phase dependency of combined L1D/L1I prefetcher and L2 replacement strategies and proposes a lightweight dynamic selection mechanism governed by a single-bit control signal, framing policy switching as an information acquisition problem. Leveraging phase-level performance analysis, execution feedback, passive memory monitoring, and counterfactual evaluation, the approach recovers 62.4%–73.4% of the oracle performance gap across diverse workloads. Notably, the Berti/Gaze combination—dynamically switching only the L1D prefetcher—nearly matches the performance of an eight-policy oracle, achieving an average IPC gap as low as 0.039%.

This work addresses the inefficiency of traditional approaches to predicting workload performance under varying memory configurations, which typically rely on time-consuming simulations or repeated measurements. The study reveals, for the first time, a predictable relationship between cycles per instruction (CPI) and maximum memory stall across diverse workloads. By leveraging hardware performance counters collected from a single native execution—combined with mechanistic insights and empirical data—the authors construct a regression model that enables highly accurate, simulation-free first-order performance prediction. Evaluated across six machine configurations and two simulators, the method reduces CPI prediction error by 2× compared to the best existing single-run techniques. On ARM servers, it achieves a median error of 12.7% and a 90th-percentile error of 35.9%, maintaining robust accuracy even when extrapolating to memory latencies up to 8× higher than baseline.

This work addresses the challenge of memory inefficiencies—such as redundant allocations and suboptimal usage—in large-scale software systems, which often lead to significant resource waste and performance degradation. Existing optimization approaches lack end-to-end automation and struggle to scale to codebases exceeding hundreds of millions of lines. To overcome this, we propose MOA, a novel framework that integrates multi-agent large language models with performance profiling data. MOA employs three coordinated agents—Analyzer, Checker Generator, and Patcher—to automatically detect memory anti-patterns, synthesize static checkers, and generate state-machine-guided, semantics-preserving patches. Evaluated on OpenHarmony’s C/C++ codebase (>100 million lines), MOA identified 13 memory anti-patterns (9 previously unknown), pinpointed over 10,000 inefficiency instances, and produced 769 patches with a 92.5% expert acceptance rate, reducing heap memory usage by 42.2% and binary size by 10.6% on average.