parallel computing frameworks

To address the lack of an efficient AI kernel development paradigm for AMD GPUs (CDNA architecture), this paper introduces HK—the first high-performance AI operator programming framework tailored for AMD. Methodologically, it systematically identifies CDNA-applicable programming primitives, designs block-based explicit memory management, fine-grained asynchronous execution, and worker-coordination mechanisms, and implements a C++-embedded domain-specific language (DSL) to establish a vendor-portable software abstraction layer. Contributions include: (1) the first AMD-specific high-performance programming model, breaking the NVIDIA-centric DSL monopoly; and (2) near-optimal or even assembly-level performance on core operators—e.g., attention (d=64) and grouped-query attention (GQA) backward pass achieve 1.2–2.4× speedup over state-of-the-art baselines, significantly outperforming compiler-generated code.

To address the bottleneck in GPGPU performance modeling—its heavy reliance on manual feature engineering and hardware simulation—this paper proposes, for the first time, an end-to-end LLM-based approach for predicting OpenCL program execution time. The method takes raw OpenCL source code as input and integrates program-structure-aware representation with a regression-based output design, eliminating the need for handcrafted features or low-level hardware simulation. The model is fine-tuned on a large-scale OpenCL source code dataset, achieving a mean absolute percentage error (MAPE) of 24.25% on a self-constructed validation set and 46.1% on a public OpenCL benchmark suite. Its core contribution lies in pioneering the application of large language models to GPGPU performance modeling, enabling fully automated, feature-free prediction from source code to runtime. This establishes a novel paradigm for compiler optimization and heterogeneous programming.

This work addresses the longstanding challenge in GPU programming of simultaneously achieving high productivity, portability, and performance: low-level models offer high performance but suffer from poor developer productivity, while high-level abstractions improve productivity at the cost of performance. To bridge this gap, the paper proposes nomp, a novel framework that integrates a pragma-based programming model with a metadata-driven runtime system to enable domain-specific code transformation and generation. By incorporating domain-specific optimization patterns, nomp significantly enhances programming productivity while preserving high performance and cross-platform portability, effectively reconciling the trade-offs between low-level efficiency and high-level abstraction in GPU programming.

GPU-based SGEMM suffers from poor performance portability, while conventional auto-tuning approaches are prone to overfitting and require costly re-tuning across devices. Method: This paper proposes a “portable tuning” framework that leverages CLBlast’s GEMM performance data to jointly orchestrate multi-versioned kernel code generation and static optimization strategies, automatically producing a lightweight, complementary set of kernel variants. Crucially, no re-tuning on target hardware is needed. Contribution/Results: The framework achieves high-performance generalization across diverse GPU architectures (e.g., NVIDIA and AMD), attaining on average 90% of theoretical peak performance across multiple GPUs—significantly outperforming CLBlast’s default kernels. It substantially reduces deployment overhead and overcomes the strong dependence of traditional auto-tuning on specific devices and input sizes.

This work addresses the challenge of automatically generating high-performance CUDA kernels tailored to GPU hardware characteristics. We propose the Feature Search and Reinforcement (FSR) framework—the first LLM-based approach enabling end-to-end kernel generation while jointly guaranteeing functional correctness, compilation success, and empirically measured latency optimality. FSR integrates hardware-aware prompting, compilation-feedback-driven reinforcement learning, real GPU latency evaluation, and multi-iteration optimization. Evaluated on AI and compute-intensive operators, FSR achieves 100% functional correctness and delivers up to 179× speedup over hand-written CUDA kernels—substantially outperforming existing LLM-based code generation methods. This work establishes a novel paradigm for LLM-driven hardware–software co-design and compiler-aware programming.

This work addresses the lack of portable memory semantics for GPU architectures in existing OpenSHMEM implementations, which has led to fragmented vendor-specific approaches. To resolve this, the authors propose a lightweight, backward-compatible auxiliary specification that, for the first time, defines a vendor-neutral GPU-scoped memory space abstraction along with a complementary capability query mechanism. This unified framework harmonizes the semantics of remote memory access (RMA), atomic operations, synchronization, and collective operations under both host-initiated and device-initiated execution models. Built upon the Partitioned Global Address Space (PGAS) paradigm, the proposal is accompanied by a prototype implementation deployable across multiple GPU vendors, thereby establishing the first practical foundation and standardization pathway for GPU extensions to the OpenSHMEM specification.

This work addresses the inefficiency of GPU kernel tuning, which traditionally relies on repeatedly recompiling full applications and manually isolating kernels—a process that is both tedious and error-prone. The authors propose an automated approach that intercepts HSA runtime dispatches to capture device memory snapshots, kernel source code, and launch configurations, thereby generating minimal, self-contained reproducer projects that can be independently compiled and validated. Their method is the first to support automatic extraction of both HIP and Triton kernels, preserving virtual address fidelity in memory snapshots and retaining JIT tuning configurations for Triton, enabling recompilation without the original build system. Evaluated across six real-world workloads, the technique successfully extracts snapshots ranging from 152 MB to 30 GB, achieving a 13.6× speedup in kernel iteration time for llama.cpp and significantly accelerating tuning and generative optimization workflows.

Traditional CGRA compilation approaches struggle to effectively exploit parallelism in computational kernels containing implicit matrix multiplication (mmul) operations, leading to suboptimal performance. This work proposes a novel compilation framework that integrates the polyhedral model with parameterized mmul scheduling. By applying loop permutation, tiling, and polyhedral transformations, the framework automatically identifies hidden mmul patterns in source code and replaces them with pre-optimized kernels, while the remaining code is compiled independently. This hybrid strategy significantly improves CGRA resource utilization, achieving up to a 9.1× speedup on various benchmarks featuring implicit mmul operations. Moreover, the approach demonstrates scalability across CGRA architectures of different sizes.

This work addresses the lack of a unified programming model in heterogeneous computing, which hinders the co-optimization of code portability, development productivity, and performance. From a developer-centric perspective, the study establishes a systematic evaluation framework to rigorously analyze the performance trade-offs between SYCL’s memory management models—Unified Shared Memory (USM) versus buffer-accessor—and its parallel execution abstractions—NDRange kernels versus hierarchical kernels—in cross-platform development scenarios. Leveraging multiple compiler implementations and empirical measurements on Intel hardware, the paper uncovers critical limitations in the current SYCL standard concerning behavioral consistency and performance portability. These findings provide empirical evidence to guide future evolution of the SYCL specification and inform optimizations in heterogeneous programming frameworks.