4. Firefly v2: Advancing hardware support for high-performance spiking neural network with a spatiotemporal fpga accelerator
5. Firefly: A high-throughput hardware accelerator for spiking neural networks with efficient dsp and memory optimization
Co-Authored Publications:
1. FireFly-S: Exploiting Dual-Side Sparsity for Spiking Neural Networks Acceleration With Reconfigurable Spatial Architecture
2. SpikePack: Enhanced Information Flow in Spiking Neural Networks with High Hardware Compatibility
3. Are Conventional SNNs Really Efficient? A Perspective from Network Quantization
4. Implementation of CNN Heterogeneous Scheme Based on Domestic FPGA with RISC-V Soft Core CPU
5. Hardware Resource and Computational Density Efficient CNN Accelerator Design Based on FPGA
Preprints:
1. FireFly-T: High-Throughput Sparsity Exploitation for Spiking Transformer Acceleration with Dual-Engine Overlay Architecture
Research Experience
Working at the Institute of Automation, Chinese Academy of Sciences.
Education
Currently pursuing a Ph.D. at the Institute of Automation, Chinese Academy of Sciences, under the supervision of Professor Yi Zeng.
Background
Research Interests: Hardware accelerators for deep learning models, specifically Large Language Models (LLMs), Convolutional Neural Networks (CNNs), and Spiking Neural Networks (SNNs). Brief Introduction: A third-year Ph.D. student at the Institute of Automation, Chinese Academy of Sciences, supervised by Professor Yi Zeng.