Scholar
Run Wang
Google Scholar ID: bOc4fcAAAAAJ
Integrated Systems Laboratory (IIS), ETHz
Citations & Impact
Citations
46
H-index
2
i10-index
1
Publications
5
Co-authors
0
Publications
Resume (English only)
Academic Achievements
- - Paper: Towards a Neuromorphic Tactile Sensing Glove
- - Paper: Hybrid RNN-ANN Based Deep Physiological Network for Pain Recognition
Research Experience
- - PhD Student: IIS ETH, Oct 2025 – present, On-Device LLM Fine-Tuning and Hardware-Software Co-Design
- - Master Thesis: IIS ETH, Jan 2025 – Jul 2025, On-Device Learning on Heterogeneous SoCs with Software-Managed Caches
- - Compiler Intern: Buddy Compiler, Jul 2024 – Oct 2024, Development of a Performance Test Suite for LLVM MLIR Compiler on RISC-V Vector Platform for LLM
- - Semester Project: IIS ETH, Feb 2024 – Jul 2024, Transformer Hardware-Software Codesign for NeuroSoc
- - Research Intern: EAST-MICAS, KUL, Jun 2023 – Sep 2022, Design and Implementation of an Electronic Skin for Prosthetics Applications
- - Intern: Alibaba, Jun 2022 – Sep 2022, Apache RocketMQ Documentation Manager & Website Development
- - Undergraduate Researcher: Fudan University, Prof. Zhongzhi Zhang, Nov 2020 – May 2021, Graph Spectral Optimization Algorithm Design
- - Undergraduate Researcher: Fudan University, Prof. Wei Chen and Prof. Hui Feng, Aug 2019 – Feb 2020, Work on Pain Classification Problem with Deep Learning Method
Education
- - M.S. in Information Technology and Electrical Engineering, 2022, ETH Zurich, specializing in digital IC architecture design and exploring machine learning applications in hardware-efficient systems
- - B.E. in Electrical Engineering (Honours), 2018-2022, Fudan University, focusing on biomedical engineering
Background
- Currently pursuing a Ph.D. at the Integrated Systems Laboratory (IIS), ETH Zurich, under the supervision of Prof. Luca Benini. Research focuses on hardware/software co-design, particularly accelerating machine learning workloads through tightly coupled hardware and compiler optimizations.
Miscellany
- Interests include Hardware & Software Co-Design, TinyML, ML Compiler
Co-authors