The work on the efficient processor for Kyber was published in Asia and South Pacific Design Automation Conference (ASP-DAC 2020).
Research Experience
Participated in a project related to wireless sensor networks during undergraduate studies; continued research at UCAS, focusing on the implementation of post-quantum cryptography. One of the works involves developing an efficient processor for a lattice-based algorithm called Kyber, which involved proposing a dual-column sequential storage scheme and implementing Gentlemen-Sande butterfly in both forward and inverse NTT computing. Another work is about a high-performance heterogeneous acceleration card for post-quantum cryptography.
Education
Ph.D. candidate at the University of Chinese Academy of Sciences, China (under the guidance of a supervisor, focusing on new lattice-based algorithms, especially those in the NIST standardization competition).
Background
Interested in hardware architecture and security. Research focuses on designing efficient processors for Post-Quantum Cryptography schemes and implementing heterogeneous platforms with FPGA acceleration cards. Future research plans also include PUF-based secure processors.
Miscellany
Looking for a suitable postdoctoral position focusing on hardware security.