Scholar
Md Mizanur Rahaman Nayan
Google Scholar ID: UbR9cx4AAAAJ
Georgia Institute of Technology
Citations & Impact
Citations
23
H-index
2
i10-index
1
Publications
9
Co-authors
9
list available
Publications
Resume (English only)
Academic Achievements
- Paper 'HyDra: A SOT-CAM based vector symbolic macro for HDC' accepted in ICCAD 2025.
- Presented research poster in DAC 2025.
- First-authored paper 'Axon' accepted for DATE'25, to be held in Lyon, France!
- Awarded CRNCH (Center for Research into Novel Compute Hierarchies) Ph.D. Fellowship.
- Journal Paper 'Frequency tunable CMOS ring oscillator-based Ising machine' accepted at Wiley International Journal of Circuit Theory and Applications.
- Awarded Silicon Creation Grant for ISSCC'24.
- Paper 'A Deep Ensemble Model with an Efficient Feature for Multi-class Arrhythmia Classification Utilizing 12-Lead ECG Signal' published in IEEE ICECE 2022.
- Paper 'Parallel Training of TN and ITN Models Through CycleGAN for Improved Sequence to Sequence Learning Performance' published in IEEE APSIPA ASC 2022.
- Paper 'An IoT Based Real-time Railway Fishplate Monitoring System for Early Warning' published in IEEE ICECE 2020.
Research Experience
- Position: ML Hardware Accelerator Research Intern; Company: Nissan Advanced Technology Center; Start Date: May 17, 2025.
Education
- Degree: Ph.D.; University: Georgia Tech; Advisor: Professor Azad J. Naeemi; Time: August 2023 - Present; Major: Nanoelectronics.
Background
- Research Interests: Novel computing hierarchies, integration of emerging memory devices, domain-specific and heterogeneous computing, optimization of digital ML hardware accelerators. Bio: A Ph.D. student in the Nanoelectronics Research Lab at Georgia Tech, dedicated to developing solutions for next-generation AI applications.
