Scholar
Zihan Liu
Google Scholar ID: UYWjK8cAAAAJ
Shanghai Jiao Tong University
Citations & Impact
Citations
263
H-index
8
i10-index
5
Publications
17
Co-authors
0
Resume (English only)
Academic Achievements
- [{'Conference': 'HPCA’25', 'PaperTitle': 'VQ-LLM: High-performance Code Generation for Vector Quantization Augmented LLM Inference', 'Authors': 'Zihan Liu, Xinhao Luo, Junxian Guo, Wentao Ni, Yangjie Zhou, Yue Guan, Cong Guo, Weihao Cui, Yu Feng, Minyi GUo, Yuhao Zhu, Minjia Zhang, Jingwen Leng, Chen Jin', 'Field': 'LLM, Quantization, Code Generation'}, {'Conference': 'HPCA’25', 'PaperTitle': 'MANT: Efficient Low-bit Group Quantization for LLMs via Mathematically Adaptive Numerical Type', 'Authors': 'Weiming Hu, Haoyan Zhang, Cong Guo, Yu Feng, Renyang Guan, Zhendong Hua, Zihan Liu, Yue Guan, Minyi Guo, Jingwen Leng', 'Field': 'LLM, Quantization, Accelerator'}, {'Conference': 'TACO’24', 'PaperTitle': 'Potamoi: Accelerating Neural Rendering via a Unified Streaming Architecture', 'Authors': 'Yu Feng, Weikai Lin, Zihan Liu, Jingwen Leng, Minyi Guo, Han Zhao, Xiaofeng Hou, Jieru Zhao, Yuhao Zhu', 'Field': 'NeRF, Accelerator'}, {'Conference': 'ISCA’24', 'PaperTitle': 'Cicero: Addressing Algorithmic and Architectural Bottlenecks in Neural Rendering by Radiance Warping and Memory Optimizations', 'Authors': 'Yu Feng, Zihan Liu, Jingwen Leng, Minyi Guo, Yuhao Zhu', 'Field': 'NeRF, Accelerator'}, {'Conference': 'ASPLOS’24', 'PaperTitle': 'JUNO: Optimizing High-Dimensional Approximate Nearest Neighbour Search with Sparsity-Aware Algorithm and Ray-Tracing Core Mapping', 'Authors': 'Zihan Liu, Wentao Ni, Jingwen Leng, Yu Feng, Cong Guo, Quan Chen, Chao Li, Minyi Guo, Yuhao Zhu', 'Field': 'Nearest Neighbor, Ray Tracing'}, {'Conference': 'ASPLOS’24', 'PaperTitle': 'GMLake: Efficient and Transparent GPU Memory Defragmentation for Large-scale DNN Training with Virtual Memory Stitching', 'Authors': 'Cong Guo, Rui Zhang, Jiale Xu, Jingwen Leng, Zihan Liu, Ziyu Huang, Minyi Guo, Hao Wu, Shouren Zhao, Junping Zhao, Ke Zhang', 'Field': 'LLM, GPU Memory'}, {'Conference': 'CF’23', 'PaperTitle': 'AdaptGear: Accelerating GNN Training via Adaptive Subgraph-Level Kernels on GPUs', 'Authors': 'Yangjie Zhou, Yaoxu Song, Jingwen Leng, Zihan Liu, Weihao Cui, Zhendong Zhang, Cong Guo, Quan Chen, Li Li, Minyi Guo', 'Field': 'GNN, Code Generation'}, {'Conference': 'MICRO’22', 'PaperTitle': 'ANT: Exploiting Adaptive Numerical Data Type for Low-bit Deep Neural Network Quantization', 'Authors': 'Cong Guo, Chen Zhang, Jingwen Leng, Zihan Liu, Fan Yang, Yunxin Liu, Minyi Guo, Yuhao Zhu', 'Field': 'LLM, Quantization, Accelerator'}, {'Conference': 'ASPLOS’22', 'PaperTitle': 'VELTAIR: Towards High-Performance Multi-tenant Deep Learning Service via Adaptive Compilation and Scheduling', 'Authors': 'Zihan Liu, Jingwen Leng, Zhihui Zhang, Quan Chen, Chao Li, Minyi Guo', 'Field': 'Code Generation, DNN Runtime'}, {'Conference': 'ISPA’20', 'PaperTitle': 'DLFusion: An Auto-Tuning Compiler for Layer Fusion on Deep Neural Networks', 'Authors': 'Zihan Liu, Jingwen Leng, Quan Chen, Chao Li, Wenli Zheng, Li Li, Minyi Guo', 'Field': 'Auto-Tuning, Compiler, Deep Neural Networks'}]
Research Experience
- [{'Title': 'Intern', 'Company': 'SAP IBSO', 'JobDescription': 'Cloud Foundry development', 'Time': '2018.08-2019.01'}, {'Title': 'Intern', 'Company': 'NVIDIA GPU SM Arch', 'JobDescription': 'CModel development', 'Time': '2019.02-2019.06'}, {'Title': 'Intern', 'Company': 'Intel IAGS', 'JobDescription': 'LLVM CodeGen', 'Time': '2020.06-2021.06'}, {'Title': 'Research Intern', 'Company': 'Shanghai Qi Zhi Institute', 'JobDescription': 'Research', 'Time': '2021.07-2022.05'}, {'Title': 'Intern', 'Company': 'AMD GFX HW MI', 'JobDescription': 'GPU IP DV(Design Verification)', 'Time': '2022.06-2022.12'}]
Background
- He is currently a Ph.D. candidate at Shanghai Jiao Tong University, Dept. of Computer Science and Engineering, SEIEE. He is supervised by Prof. Jingwen Leng and mainly researches on computer architecture, AI system, compiler, and optimization. His broad interests include chip design, compiler optimization, computer organization, and system architecture.
Miscellany
- No additional information provided
Co-authors