Scholar
George Bisbas
Google Scholar ID: TLBXIugAAAAJ
Imperial College London
HPC
stencils
performance benchmarking
DSLs
compilation
Follow
Homepage
↗
Google Scholar
↗
Citations & Impact
All-time
Citations
24
H-index
3
i10-index
0
Publications
15
Co-authors
19
list available
Contact
No contact links provided.
Publications
3 items
An MLIR Lowering Pipeline for Stencils at Wafer-Scale
2026
Cited
0
A shared compilation stack for distributed-memory parallelism in stencil DSLs
International Conference on Architectural Support for Programming Languages and Operating Systems · 2024
Cited
4
Automated MPI-X code generation for scalable finite-difference solvers
2023
Cited
2
Resume (English only)
Co-authors
19 total
Co-author 1
Co-author 2
Co-author 3
Paul Kelly
Professor of Software Technology, Imperial College London
Philipp A. Witte
Microsoft AI
Co-author 6
Felix J. Herrmann
Professor Schools of Earth and Atmospheric Sciences, Computational Science and Engineering
Tobias Grosser
University of Cambridge
×
Welcome back
Sign in to Agora
Welcome back! Please sign in to continue.
Email address
Password
Forgot password?
Continue
Do not have an account?
Sign up