Zhengyuan Shi (石正源)
Scholar

Zhengyuan Shi (石正源)

Google Scholar ID: SQaM_UMAAAAJ
PhD Candidate, The Chinese University of Hong Kong
Large Circuit ModelEDASAT/SMT
Citations & Impact
All-time
Citations
355
 
H-index
11
 
i10-index
11
 
Publications
20
 
Co-authors
14
list available
Publications
20 items
Browse publications on Google Scholar (top-right) ↗
Resume (English only)
Academic Achievements
  • Published more than 20 papers at top EDA conferences and journals, including DAC, ICCAD, DATE, and ASPDAC. Served as a reviewer for DAC, ICCAD, TVLSI, Sci China Inf Sci, and others. Presented papers at multiple international conferences, including ASP-DAC, ICCAD, CP, and DAC. Won several awards, including the 3rd prize in the Main Track of the SAT Competition.
Research Experience
  • Gained valuable experience as an intern at Huawei, Hisilicon, and Xilinx, and also worked as a visiting student at CityU and UBC.
Education
  • Obtained B.Eng. degree with presidential scholarship from Shandong University in 2021, supervised by Prof. Gangqiang Yang; currently pursuing a Ph.D. at CUHK, supervised by Prof. Qiang Xu.
Background
  • Research Interests: AI for EDA, including Large Circuit Model, Logic Synthesis and Formal Verification; AI for Optimization Problems, such as SAT/SMT, MaxSAT, ILP. Background: Zhengyuan Shi is a Ph.D. Candidate in the Department of Computer Science and Engineering at The Chinese University of Hong Kong (CUHK), supervised by Prof. Qiang Xu.
Miscellany
  • Looking for job opportunities, expected to graduate in Dec. 2025.