Scholar
Cheng Tan
Google Scholar ID: NUbYZ50AAAAJ
Google, Arizona State University
Citations & Impact
Citations
990
H-index
19
i10-index
28
Publications
20
Co-authors
7
list available
Publications
Resume (English only)
Academic Achievements
- Published papers as the first author across all top-tier architecture conferences (ISCA/MICRO/HPCA/ASPLOS/DAC/DATE/ICCAD/ASP-DAC). Best Paper Award at IEEE Micro (2022) and ICCD (2021). Nominated for Best Paper at CASES (2016). Open-source projects include CGRA-Flow, CGRA-Mapper, MLIR-CGRA, and more.
Research Experience
- Employed by Microsoft, Pacific Northwest National Laboratory, and Cornell University, working on Brainwave Machine Learning Accelerator/Compiler, HW/SW co-design, and Network-on-Chip, respectively.
Education
- Received Ph.D. from the National University of Singapore.
Background
- Currently a software engineer at Google working on Edge TPU machine learning compiler. Also a research faculty at Arizona State University. Research interests include: Machine Learning Compiler, Many-Core Architecture, Hardware/Software Co-Design, Reconfigurable Accelerator, and Network-on-Chip.
Miscellany
- Dedicated to democratizing domain-specific reconfigurable acceleration, aiming at a push-button solution towards compilation, system and architecture design, synthesis, and tape-out. Most of my research works are open-source at https://github.com/tancheng. Open to research collaboration.
