Scholar
Partha Pande
Google Scholar ID: LcbWF44AAAAJ
Washington State University
Citations & Impact
Citations
3,427
H-index
30
i10-index
95
Publications
20
Co-authors
63
list available
Contact
Publications
Browse publications on Google Scholar (top-right) ↗
Resume (English only)
Academic Achievements
- Editor-in-Chief (EIC) of IEEE Design and Test (D&T); Editorial boards of IEEE Transactions on VLSI (TVLSI), ACM Journal of Emerging Technologies in Computing Systems (JETC), and IEEE Embedded Systems letters; Technical Program Committee Chair of IEEE/ACM Network-on-Chip Symposium 2015 and CASES (2019-2020); Serves on program committees of many reputed international conferences; NSF CAREER award winner in 2009; Anjan Bose outstanding researcher award from the college of engineering, Washington State University in 2013; Fellow of IEEE.
Research Experience
- Currently, the Director at MARS Lab, which focuses on Manycore Architecture and Systems Research exploring projects from edge devices to cloud to advance hardware designs, enabling a cycle of ML techniques for further advances in ML (a.k.a. ML for ML). Research areas include Fault-Tolerant PIM accelerator, Dynamic Resource Management, Chiplet-based Architecture Design, and DNN Training and Graph Learning at the Edge.
Education
- Insufficient information
Background
- Professor and holder of the Boeing Centennial Chair in computer engineering at the School of Electrical Engineering and Computer Science, Washington State University, Pullman, USA. Currently, the director of the school. His current research interests are novel interconnect architectures for manycore chips, on-chip wireless communication networks, heterogeneous architectures, and ML for EDA.
