Marc Riedel
Scholar

Marc Riedel

Google Scholar ID: JYD7wcgAAAAJ
Full Professor of Electrical and Computer Engineering, University of Minnesota
Logic SynthesisLogic VerificationFormal VerificationSynthetic BiologyMolecular Computing
Homepage↗Google Scholar↗
Citations & Impact
All-time
Citations
5,116
 
H-index
39
 
i10-index
50
 
Publications
20
 
Co-authors
58
list available
Contact
No contact links provided.
Publications
1 items
Maximizing Memory-Level Parallelism via Integrated Stochastic Logic-in-Memory Architectures
2026
Cited
0
Resume (English only)
Co-authors
58 total
Co-author 1
Co-author 1
Weikang Qian
Weikang Qian
University of Michigan-SJTU Joint Institute, Shanghai Jiao Tong University
Kia Bazargan
Kia Bazargan
Associate Professor of ECE, University of Minnesota
Jehoshua Bruck
Jehoshua Bruck
Gordon and Betty Moore Professor, Emeritus, Caltech
Keshab K. Parhi
Keshab K. Parhi
University of Minnesota, Erwin A. Kelen Chair in Electrical Engineering
Co-author 6
Co-author 6
M. Hassan Najafi
M. Hassan Najafi
Associate Professor, ECSE Department, Case Western Reserve University
Co-author 8
Co-author 8