Scholar
Jianyi Cheng
Google Scholar ID: HfOtGc0AAAAJ
University of Edinburgh
Citations & Impact
Citations
507
H-index
11
i10-index
12
Publications
20
Co-authors
6
list available
Publications
Resume (English only)
Academic Achievements
- Published 'Adaptive CHERI Compartmentalization for Heterogeneous Accelerators' at ISCA 2025
- Published 'SEER: Super-Optimization Explorer for High-Level Synthesis using E-Graph Rewriting' at ASPLOS 2024
- Published 'Balancing Static Islands in Dynamically Scheduled Circuits using Continuous Petri Nets' in IEEE TC 2023
- Published 'Dynamic C-Slow Pipelining for HLS' at FCCM 2022
- Published 'Efficient Memory Arbitration in High-Level Synthesis from Multi-Threaded Code' in IEEE TC 2021
- Published 'Combining Dynamic & Static Scheduling in High-Level Synthesis' at FPGA 2020
