Co-author of over 100 scientific publications in international conferences and journals
Program Chair of DFT Symposium in 2016 and 2017
DATE Topic Chair (2018–2021, 2026); Interactive Presentation Chair in 2022
Associate Editor for IEEE Transactions on VLSI Systems and Elsevier Microprocessors and Microsystems
Guest co-Editor of two special issues on fault tolerance: IEEE Transactions on Emerging Topics in Computing (published 2020) and IET Computers & Digital Techniques (published 2019)
TPC member for conferences including DATE, DFT, FPL, IOLTS, ARC, DSD
Research Experience
Postdoc Research Assistant at Politecnico di Milano (2010–2014)
Assistant Professor at Politecnico di Milano (2014–2021)
Associate Professor at Politecnico di Milano (2021–present)
Participated in national and EU-funded projects: FP7 STREP 'SAVE' (2013–2016), EU-ARTEMIS 'SMECY' (2010–2013) and 'SCALOPES' (2009–2010), MIUR-PRIN 2008 project (2010–2012)
Recent research supported by Intel Corporation (fault tolerance for image processing and ML) and Huawei (runtime resource management in edge systems)
Current research includes dependable computing systems, dependability of deep learning systems, error modeling/simulation, and hardening techniques for image processing and deep learning applications