Scholar
Mahesh A. Iyer
Google Scholar ID: 2G_FW_QAAAAJ
Intel Corporation
Electronic Design Automation
ASIC
FPGA
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Citations & Impact
All-time
Citations
464
H-index
10
i10-index
10
Publications
20
Co-authors
0
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Publications
1 items
Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage
2025
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0
Resume (English only)
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0 total
Co-authors: 0 (list not available)
