Scholar

Mahesh A. Iyer

Google Scholar ID: 2G_FW_QAAAAJ

Intel Corporation

Electronic Design AutomationASICFPGA

Google Scholar↗

Citations & Impact

All-time

Citations

464

H-index

10

i10-index

10

Publications

20

Co-authors

0

Contact

No contact links provided.

Publications

1 items

Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage

2025

Cited

0

Resume (English only)

Co-authors

0 total

Co-authors: 0 (list not available)