SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding

2025-10-20

AI Summary

Existing RTL synthesis tools (e.g., Yosys) rely solely on control-signal traversal for multiplexer (MUX) tree optimization, making them incapable of detecting and eliminating structural redundancies arising from implicit logical relationships—such as equivalence, implication, or controllability—among input signals. Method: We propose a logic-inference–driven MUX tree optimization framework that first automatically identifies MUX tree topology, then applies Boolean reasoning to uncover equivalence, implication, and don’t-care relationships among inputs, guiding targeted structural simplification and remapping; optimization is evaluated in closed loop using an AIG-area model. Contribution/Results: Evaluated on IWLS-2005 and RISC-V benchmarks, our method reduces average AIG area by 8.95% over Yosys. On million-gate industrial circuits, it achieves a 47.2% improvement in redundant-MUX removal rate, significantly enhancing area efficiency.

Technology Category

• Machine Learning: Optimization
• Search and Optimization: Mixed Discrete/Continuous Search
• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories

Application Category

• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems

Abstract

This paper proposes smaRTLy: a new optimization technique for multiplexers in Register-Transfer Level (RTL) logic synthesis. Multiplexer trees are very common in RTL designs, and traditional tools like Yosys optimize them by traversing the tree and monitoring control port values. However, this method does not fully exploit the intrinsic logical relationships among signals or the potential for structural optimization. To address these limitations, we develop innovative strategies to remove redundant multiplexer trees and restructure the remaining ones, significantly reducing the overall gate count. We evaluate smaRTLy on the IWLS-2005 and RISC-V benchmarks, achieving an additional 8.95% reduction in AIG area compared to Yosys. We also evaluate smaRTLy on an industrial benchmark in the scale of millions of gates, results show that smaRTLy can remove 47.2% more AIG area than Yosys. These results demonstrate the effectiveness of our logic inferencing and structural rebuilding techniques in enhancing the RTL optimization process, leading to more efficient hardware designs.

Problem

• Optimizes multiplexer trees in RTL logic synthesis
• Reduces redundant multiplexer trees using logic inferencing
• Restructures multiplexer trees to decrease overall gate count

Innovation

• Uses logic inferencing to remove redundant multiplexer trees
• Restructures remaining multiplexers to reduce gate count
• Enhances RTL optimization with structural rebuilding techniques