🤖 AI Summary
Existing open-source DRAM research platforms suffer from outdated architectures, limited vendor/interface support, poor usability, and insufficient extensibility, hindering low-level empirical studies on modern DRAM chips across performance, reliability, security, and energy efficiency. This paper introduces the first integrated open-source FPGA platform enabling (i) direct, command-level fine-grained control of DRAM devices; (ii) high-level C++/Python APIs for rapid experimentation; and (iii) seamless portability across heterogeneous FPGA families (Xilinx and Intel) and memory interfaces. Built upon a modular RTL design, it fully implements DDR3/DDR4 protocol stacks and has been successfully deployed on five distinct FPGA boards. Three case studies demonstrate its versatility: two reveal, for the first time, that RowHammer can induce significantly larger-scale bit flips under generalized data patterns—providing novel insights for DRAM security mechanism design.
📝 Abstract
To understand and improve DRAM performance, reliability, security, and energy efficiency, prior works study characteristics of commodity DRAM chips. Unfortunately, state-of-the-art open source infrastructures capable of conducting such studies are obsolete, poorly supported, or difficult to use, or their inflexibility limits the types of studies they can conduct. We propose DRAM Bender, a new FPGA-based infrastructure that enables experimental studies on state-of-the-art DRAM chips. DRAM Bender offers three key features at the same time. First, DRAM Bender enables directly interfacing with a DRAM chip through its low-level interface. This allows users to issue DRAM commands in arbitrary order and with finer-grained time intervals compared to other open source infrastructures. Second, DRAM Bender exposes easy-to-use C++ and Python programm ing interfaces, allowing users to quickly and easily develop different types of DRAM experiments. Third, DRAM Bender is easily extensible. The modular design of DRAM Bender allows extending it to: 1) support existing and emerging DRAM interfaces and 2) run on new commercial or custom FPGA boards with little effort. To demonstrate that DRAM Bender is a versatile infrastructure, we conduct three case studies, two of which lead to new observations about the DRAM RowHammer vulnerability. In particular, we show that data patterns supported by DRAM Bender uncover a larger set of bit-flips on a victim row than those commonly used by prior work. We demonstrate the extensibility of DRAM Bender by implementing it on five different FPGAs with DDR4 and DDR3 support. DRAM Bender is freely and openly available at https://github.com/CMU-SAFARI/DRAM-Bender.
