Honest to a Fault: Root-Causing Fault Attacks with Pre-Silicon RISC Pipeline Characterization

2025-03-05

AI Summary

This work addresses cross-layer fault propagation in RISC-V processors under clock glitching attacks, which induces severe misclassification in AI/ML applications. We propose a fine-grained pre-silicon fault attribution methodology. Leveraging RTL-level simulation and a customized fault-injection platform—integrated with timing-aware co-modeling of circuit, microarchitecture, and software—we first identify the instruction decode stage as highly vulnerable to specific glitch parameters. Furthermore, we establish a reproducible, end-to-end fault propagation tracing framework spanning from the circuit layer to the AI application layer. Our approach enables precise root-cause localization and quantitative attribution of fault propagation paths. To the best of our knowledge, this is the first scalable, pre-silicon, cross-layer fault analysis methodology specifically designed for AI workloads, thereby advancing hardware security verification for ML-accelerated systems.

Technology Category

• Machine Learning: Hardware-aware ML
• Computer Vision: Adversarial Attacks & Robustness
• Knowledge Representation and Reasoning: Diagnosis and Abductive Reasoning

Application Category

• Security and Privacy: Security and privacy of machine learning and AI applications
• User Modeling, Personalization and Recommendation: Attacks and countermeasures in recommendation systems
• Responsible Web: Machine-in-the-loop, human agency and autonomy

Abstract

Fault injection attacks represent a class of threats that can compromise embedded systems across multiple layers of abstraction, such as system software, instruction set architecture (ISA), microarchitecture, and physical implementation. Early detection of these vulnerabilities and understanding their root causes along with their propagation from the physical layer to the system software is critical to secure the cyberinfrastructure. This present presents a comprehensive methodology for conducting controlled fault injection attacks at the pre-silicon level and an analysis of the underlying system for root-causing behavior. As the driving application, we use the clock glitch attacks in AI/ML applications for critical misclassification. Our study aims to characterize and diagnose the impact of faults within the RISC-V instruction set and pipeline stages, while tracing fault propagation from the circuit level to the AI/ML application software. This analysis resulted in discovering a novel vulnerability through controlled clock glitch parameters, specifically targeting the RISC-V decode stage.

Problem

• Detect vulnerabilities in embedded systems from physical to software layers.
• Analyze fault propagation in RISC-V pipeline stages and AI/ML applications.
• Identify novel vulnerabilities in RISC-V decode stage via clock glitch attacks.

Innovation

• Pre-silicon fault injection methodology
• RISC-V pipeline fault characterization
• Clock glitch vulnerability discovery