The Case for Persistent CXL switches

2025-03-06

AI Summary

CXL-expanded memory increases capacity but incurs 170–400 ns additional latency, severely degrading crash-consistency performance in persistent memory applications. To address this, we propose the first CXL switch architecture natively supporting data persistence. Our approach introduces: (1) a system-agnostic, hardware-managed persistent buffer (PB) that truncates the write path and guarantees atomic persistence; and (2) a read-forwarding mechanism built upon an extended CXL protocol to minimize remote accesses to persistent domains. Evaluation shows the PB alone improves performance by 12% on average; with read forwarding, end-to-end speedup reaches 15%. Crucially, our design reduces persistence latency without compromising strong consistency or application transparency—enabling high-performance, crash-consistent CXL memory systems.

Technology Category

• Machine Learning: Life-Long and Continual Learning
• Search and Optimization: Distributed Search
• Data Mining & Knowledge Management: Scalability, Parallel & Distributed Systems

Application Category

• Responsible Web: Data and user privacy-enhancing technologies for the Web
• Systems and Infrastructure for Web, Mobile and WoT: Data management and stream processing for Web, mobile and wireless applications
• Security and Privacy: Privacy-enhancing technologies

Abstract

Compute Express Link (CXL) switch allows memory extension via PCIe physical layer to address increasing demand for larger memory capacities in data centers. However, CXL attached memory introduces 170ns to 400ns memory latency. This becomes a significant performance bottleneck for applications that host data in persistent memory as all updates, after traversing the CXL switch, must reach persistent domain to ensure crash consistent updates.We make a case for persistent CXL switch to persist updates as soon as they reach the switch and hence significantly reduce latency of persisting data. To enable this, we presented a system independent persistent buffer (PB) design that ensures data persistency at CXL switch. Our PB design provides 12% speedup, on average, over volatile CXL switch. Our extit{read forwarding} optimization improves speedup to 15%.

Problem

• Address high memory latency in CXL switches
• Propose persistent CXL switch for faster data updates
• Introduce persistent buffer design to reduce latency

Innovation

• Persistent CXL switch reduces memory latency.
• System-independent persistent buffer design implemented.
• Read forwarding optimization enhances performance by 15%.