Exploring LLM-based Verilog Code Generation with Data-Efficient Fine-Tuning and Testbench Automation

2026-04-16

AI Summary

This work addresses the scarcity of high-quality training data and testbenches that limits large language models in Verilog code generation. To overcome this challenge, the authors propose a multi-agent collaborative framework for automated testbench generation, enabling the construction of fine-tuning datasets with high coverage and reliability. This approach represents the first application of multi-agent systems to hardware description language generation tasks. By leveraging synergistic interactions among specialized agents, the method significantly reduces reliance on extensive training data while achieving performance on par with state-of-the-art techniques on the VerilogEval v2 benchmark, thereby demonstrating a data-efficient pathway for Verilog code synthesis.

Technology Category

• Natural Language Processing: Code Generation / Program Synthesis from Natural Language
• Multiagent Systems: Multiagent Learning
• Cognitive Modeling & Cognitive Systems: Agent Architectures

Application Category

• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems
• Semantics and Knowledge: Data modeling to support human-machine intelligence, including LLMs agents, intelligent system behavior, explanations, and user-friendly interactions
• Search and Retrieval-Augmented AI: Agentic search

Abstract

Recent advances in large language models have improved code generation, but their use in hardware description languages is still limited. Moreover, training data and testbenches for these models are often scarce. This paper presents a workflow that uses multi-agent models to generate testbenches for high-quality fine-tuning data. By automating testbench creation, the fine-tuned model for the specification-to-Verilog task achieves performance comparable to state-of-the-art methods on the refined VerilogEval v2 benchmark while using less training data. This study provides a basis for future work on LLM-based HDL generation and automated verification.

Problem

• LLM
• Verilog
• code generation
• testbench
• data scarcity

Innovation

• LLM-based Verilog generation
• data-efficient fine-tuning
• testbench automation
• multi-agent models
• hardware description language