See it to Place it: Evolving Macro Placements with Vision-Language Models

2026-03-30

AI Summary

This work addresses the challenge of macro placement in chip physical design, which requires balancing wirelength and spatial constraints—a problem poorly handled by conventional methods. The authors propose a novel approach that leverages an off-the-shelf, unfinetuned vision-language model (VLM) to guide a baseline placer by exploiting its inherent spatial reasoning capabilities for macro placement within subregions. This is combined with evolutionary search to iteratively refine the layout. The framework is highly generalizable and seamlessly integrates with both learning-based and analytical placers, such as DREAMPlace. Evaluated on ten open-source benchmarks, the method outperforms the current best learning-based approaches on nine, reducing wirelength by up to 32%. Furthermore, it consistently enhances DREAMPlace across all eight tested cases, achieving performance gains of up to 4.3%.

Abstract

We propose using Vision-Language Models (VLMs) for macro placement in chip floorplanning, a complex optimization task that has recently shown promising advancements through machine learning methods. Because human designers rely heavily on spatial reasoning to arrange components on the chip canvas, we hypothesize that VLMs with strong visual reasoning abilities can effectively complement existing learning-based approaches. We introduce VeoPlace (Visual Evolutionary Optimization Placement), a novel framework that uses a VLM, without any fine-tuning, to guide the actions of a base placer by constraining them to subregions of the chip canvas. The VLM proposals are iteratively optimized through an evolutionary search strategy with respect to resulting placement quality. On open-source benchmarks, VeoPlace outperforms the best prior learning-based approach on 9 of 10 benchmarks with peak wirelength reductions exceeding 32%. We further demonstrate that VeoPlace generalizes to analytical placers, improving DREAMPlace performance on all 8 evaluated benchmarks with gains up to 4.3%. Our approach opens new possibilities for electronic design automation tools that leverage foundation models to solve complex physical design problems.

Problem

• macro placement
• chip floorplanning
• physical design
• electronic design automation
• wirelength optimization

Innovation

• Vision-Language Models
• Macro Placement
• Evolutionary Optimization
• Chip Floorplanning
• Electronic Design Automation