Physical Design of UET-RVMCU: A Streamlined Open-Source RISC-V Microcontroller

📅 2026-03-30
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🤖 AI Summary
This work proposes an efficient methodology for transforming application-grade RISC-V SoCs into lightweight, open-source microcontrollers. Building upon the UETRV-PCore platform, the design streamlines the pipeline, removes the memory management unit (MMU), and integrates GPIO peripherals to yield a low-area RISC-V MCU tailored for embedded systems. The entire physical implementation is carried out using a fully open-source RTL-to-GDS flow based on OpenLane, successfully producing a GDSII layout. This study presents the first complete open-source pathway for converting high-performance SoCs into highly usable and flexible embedded microcontrollers, significantly reducing hardware overhead while preserving functional utility.

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📝 Abstract
This paper presents the design and physical implementation of UET-RVMCU, a lightweight RISC-V microcontroller derived from the UETRV-PCore. Aimed at creating an accessible and flexible open-source RISC-V-based microcontroller, UET-RVMCU simplifies the application-class UETRV-PCore by reducing pipeline stages, removing MMU functionality, and integrating GPIO peripherals. The final GDSII layout was generated using an open-source RTL-to-GDS flow (OpenLane). This project demonstrates the feasibility of transforming an application-class SoC into a feature-rich microcontroller suitable for embedded systems, emphasizing low area, design simplicity, and open-source development.
Problem

Research questions and friction points this paper is trying to address.

RISC-V
microcontroller
physical design
open-source
embedded systems
Innovation

Methods, ideas, or system contributions that make the work stand out.

RISC-V
open-source
microcontroller
physical design
OpenLane