KLiNQ: Knowledge Distillation-Assisted Lightweight Neural Network for Qubit Readout on FPGA

📅 2025-03-05
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🤖 AI Summary
Slow and error-prone readout of superconducting qubits limits high-fidelity quantum operations and mid-circuit measurements. Method: We propose a lightweight neural network architecture optimized for FPGA deployment, introducing knowledge distillation—applied here for the first time—to compress quantum readout models and enable single-qubit dedicated discriminators. Our approach integrates a compact CNN design, hardware-software co-optimization targeting Xilinx UltraScale+ FPGAs, and a low-latency inference pipeline. Contribution/Results: Compared to conventional deep networks, our model reduces parameter count by 99%, achieves a per-qubit discrimination latency of only 32 ns, and attains 91% classification accuracy. It supports high-speed, independent, and scalable parallel readout across multiple qubits. This addresses the dual requirements of real-time processing and hardware efficiency essential for practical quantum error correction.

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📝 Abstract
Superconducting qubits are among the most promising candidates for building quantum information processors. Yet, they are often limited by slow and error-prone qubit readout -- a critical factor in achieving high-fidelity operations. While current methods, including deep neural networks, enhance readout accuracy, they typically lack support for mid-circuit measurements essential for quantum error correction, and they usually rely on large, resource-intensive network models. This paper presents KLiNQ, a novel qubit readout architecture leveraging lightweight neural networks optimized via knowledge distillation. Our approach achieves around a 99% reduction in model size compared to the baseline while maintaining a qubit-state discrimination accuracy of 91%. KLiNQ facilitates rapid, independent qubit-state readouts that enable mid-circuit measurements by assigning a dedicated, compact neural network for each qubit. Implemented on the Xilinx UltraScale+ FPGA, our design can perform the discrimination within 32ns. The results demonstrate that compressed neural networks can maintain high-fidelity independent readout while enabling efficient hardware implementation, advancing practical quantum computing.
Problem

Research questions and friction points this paper is trying to address.

Improves qubit readout speed and accuracy
Enables mid-circuit measurements for error correction
Reduces model size for efficient FPGA implementation
Innovation

Methods, ideas, or system contributions that make the work stand out.

Lightweight neural networks via knowledge distillation
Dedicated compact neural network per qubit
FPGA implementation with 32ns discrimination time
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